From e925927e2361ebdd398679754913e91fceecd431 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 12:05:57 -0500 Subject: [PATCH] target/riscv: narrowing floating-point/integer type-convert instructions Backports 878d406ec28f945d262af4ffbea50b825d7a0825 --- qemu/header_gen.py | 10 ++++ qemu/riscv32.h | 10 ++++ qemu/riscv64.h | 10 ++++ qemu/target/riscv/helper.h | 11 +++++ qemu/target/riscv/insn32.decode | 5 ++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 49 ++++++++++++++++++++ qemu/target/riscv/vector_helper.c | 39 ++++++++++++++++ 7 files changed, 134 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index b20ce144..48d11260 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7191,6 +7191,16 @@ riscv_symbols = ( 'helper_vfwcvt_f_x_v_w', 'helper_vfwcvt_f_f_v_h', 'helper_vfwcvt_f_f_v_w', + 'helper_vfncvt_xu_f_v_h', + 'helper_vfncvt_xu_f_v_w', + 'helper_vfncvt_x_f_v_h', + 'helper_vfncvt_x_f_v_w', + 'helper_vfncvt_f_xu_v_h', + 'helper_vfncvt_f_xu_v_w', + 'helper_vfncvt_f_x_v_h', + 'helper_vfncvt_f_x_v_w', + 'helper_vfncvt_f_f_v_h', + 'helper_vfncvt_f_f_v_w', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 378eb906..9ad68ee8 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4627,6 +4627,16 @@ #define helper_vfwcvt_f_x_v_w helper_vfwcvt_f_x_v_w_riscv32 #define helper_vfwcvt_f_f_v_h helper_vfwcvt_f_f_v_h_riscv32 #define helper_vfwcvt_f_f_v_w helper_vfwcvt_f_f_v_w_riscv32 +#define helper_vfncvt_xu_f_v_h helper_vfncvt_xu_f_v_h_riscv32 +#define helper_vfncvt_xu_f_v_w helper_vfncvt_xu_f_v_w_riscv32 +#define helper_vfncvt_x_f_v_h helper_vfncvt_x_f_v_h_riscv32 +#define helper_vfncvt_x_f_v_w helper_vfncvt_x_f_v_w_riscv32 +#define helper_vfncvt_f_xu_v_h helper_vfncvt_f_xu_v_h_riscv32 +#define helper_vfncvt_f_xu_v_w helper_vfncvt_f_xu_v_w_riscv32 +#define helper_vfncvt_f_x_v_h helper_vfncvt_f_x_v_h_riscv32 +#define helper_vfncvt_f_x_v_w helper_vfncvt_f_x_v_w_riscv32 +#define helper_vfncvt_f_f_v_h helper_vfncvt_f_f_v_h_riscv32 +#define helper_vfncvt_f_f_v_w helper_vfncvt_f_f_v_w_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index e8b6711f..a4ceb488 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4627,6 +4627,16 @@ #define helper_vfwcvt_f_x_v_w helper_vfwcvt_f_x_v_w_riscv64 #define helper_vfwcvt_f_f_v_h helper_vfwcvt_f_f_v_h_riscv64 #define helper_vfwcvt_f_f_v_w helper_vfwcvt_f_f_v_w_riscv64 +#define helper_vfncvt_xu_f_v_h helper_vfncvt_xu_f_v_h_riscv64 +#define helper_vfncvt_xu_f_v_w helper_vfncvt_xu_f_v_w_riscv64 +#define helper_vfncvt_x_f_v_h helper_vfncvt_x_f_v_h_riscv64 +#define helper_vfncvt_x_f_v_w helper_vfncvt_x_f_v_w_riscv64 +#define helper_vfncvt_f_xu_v_h helper_vfncvt_f_xu_v_h_riscv64 +#define helper_vfncvt_f_xu_v_w helper_vfncvt_f_xu_v_w_riscv64 +#define helper_vfncvt_f_x_v_h helper_vfncvt_f_x_v_h_riscv64 +#define helper_vfncvt_f_x_v_w helper_vfncvt_f_x_v_w_riscv64 +#define helper_vfncvt_f_f_v_h helper_vfncvt_f_f_v_h_riscv64 +#define helper_vfncvt_f_f_v_w helper_vfncvt_f_f_v_w_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index d8737110..99082e45 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1031,3 +1031,14 @@ DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index eda09f0c..55fbe166 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -526,6 +526,11 @@ vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm +vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm +vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm +vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm +vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm +vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 18de909a..146eddca 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2312,3 +2312,52 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) + +/* Narrowing Floating-Point/Integer Type-Convert Instructions */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ +static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, true) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, + 2 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +#define GEN_OPFV_NARROW_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + TCGContext *tcg_ctx = s->uc->tcg_ctx; \ + if (opfv_narrow_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[2] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(tcg_ctx); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(tcg_ctx, over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index b680fd34..06aa5092 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4269,3 +4269,42 @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16) RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4, clearl) GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq) + +/* Narrowing Floating-Point/Integer Type-Convert Instructions */ +/* (TD, T2, TX2) */ +#define NOP_UU_H uint16_t, uint32_t, uint32_t +#define NOP_UU_W uint32_t, uint64_t, uint64_t +/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ +RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl) + +/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ +RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl) + +/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ +RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl) + +/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ +RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl) + +/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ +static uint16_t vfncvtffv16(uint32_t a, float_status *s) +{ + return float32_to_float16(a, true, s); +} + +RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)