From ebc7b9371fbb3049cddd39ca0322ad19ceddea93 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 22 Mar 2020 01:29:35 -0400 Subject: [PATCH] target/riscv: Add virtual register swapping function Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu --- qemu/header_gen.py | 1 + qemu/riscv32.h | 1 + qemu/riscv64.h | 1 + qemu/target/riscv/cpu.h | 11 ++++++ qemu/target/riscv/cpu_bits.h | 7 ++++ qemu/target/riscv/cpu_helper.c | 61 ++++++++++++++++++++++++++++++++++ 6 files changed, 82 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 48007f5f..3524bd52 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -5575,6 +5575,7 @@ riscv_symbols = ( 'riscv_cpu_set_force_hs_excep', 'riscv_cpu_set_mode', 'riscv_cpu_set_virt_enabled', + 'riscv_cpu_swap_hypervisor_regs', 'riscv_cpu_tlb_fill', 'riscv_cpu_unassigned_access', 'riscv_cpu_update_mip', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 0de0315d..290eb319 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -3462,6 +3462,7 @@ #define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv32 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32 #define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv32 +#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv32 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32 #define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv32 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index ddb63260..b77b8e12 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -3462,6 +3462,7 @@ #define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv64 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64 #define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv64 +#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv64 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64 #define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv64 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64 diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index 8d4bd0ca..f996478f 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -140,6 +140,7 @@ struct CPURISCVState { * mip is 32-bits to allow atomic_read on 32-bit hosts. */ target_ulong mip; + uint32_t miclaim; target_ulong mie; @@ -181,6 +182,15 @@ struct CPURISCVState { target_ulong mtval2; target_ulong mtinst; + /* HS Backup CSRs */ + target_ulong stvec_hs; + target_ulong sscratch_hs; + target_ulong sepc_hs; + target_ulong scause_hs; + target_ulong stval_hs; + target_ulong satp_hs; + target_ulong mstatus_hs; + target_ulong scounteren; target_ulong mcounteren; @@ -296,6 +306,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h index 27cbadc5..bfb68332 100644 --- a/qemu/target/riscv/cpu_bits.h +++ b/qemu/target/riscv/cpu_bits.h @@ -555,4 +555,11 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_UEIE (1 << IRQ_U_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_UTIE (1 << IRQ_U_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) +#define MIE_USIE (1 << IRQ_U_SOFT) #endif diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index d98cef8e..094fed76 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -72,6 +72,67 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + bool current_virt = riscv_cpu_virt_enabled(env); + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |= MSTATUS64_UXL; +#endif + + if (current_virt) { + /* Current V=1 and we are about to change to V=0 */ + env->vsstatus = env->mstatus & mstatus_mask; + env->mstatus &= ~mstatus_mask; + env->mstatus |= env->mstatus_hs; + + env->vstvec = env->stvec; + env->stvec = env->stvec_hs; + + env->vsscratch = env->sscratch; + env->sscratch = env->sscratch_hs; + + env->vsepc = env->sepc; + env->sepc = env->sepc_hs; + + env->vscause = env->scause; + env->scause = env->scause_hs; + + env->vstval = env->sbadaddr; + env->sbadaddr = env->stval_hs; + + env->vsatp = env->satp; + env->satp = env->satp_hs; + } else { + /* Current V=0 and we are about to change to V=1 */ + env->mstatus_hs = env->mstatus & mstatus_mask; + env->mstatus &= ~mstatus_mask; + env->mstatus |= env->vsstatus; + + env->stvec_hs = env->stvec; + env->stvec = env->vstvec; + + env->sscratch_hs = env->sscratch; + env->sscratch = env->vsscratch; + + env->sepc_hs = env->sepc; + env->sepc = env->vsepc; + + env->scause_hs = env->scause; + env->scause = env->vscause; + + env->stval_hs = env->sbadaddr; + env->sbadaddr = env->vstval; + + env->satp_hs = env->satp; + env->satp = env->vsatp; + } +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) {