diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h index f4306dce..531123e6 100644 --- a/qemu/include/qom/cpu.h +++ b/qemu/include/qom/cpu.h @@ -121,6 +121,15 @@ typedef struct TcgCpuOperations { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); + /** + * @do_transaction_failed: Callback for handling failed memory transactions + * (ie bus faults or external aborts; not MMU faults) + */ + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + } TcgCpuOperations; /** @@ -135,8 +144,6 @@ typedef struct TcgCpuOperations { * (this is deprecated: new targets should use do_transaction_failed instead) * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. - * @do_transaction_failed: Callback for handling failed memory transactions - * (ie bus faults or external aborts; not MMU faults) * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -181,10 +188,6 @@ typedef struct CPUClass { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, - unsigned size, MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, @@ -734,7 +737,6 @@ void cpu_interrupt(CPUState *cpu, int mask); #endif /* USER_ONLY */ -#ifdef CONFIG_SOFTMMU static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, bool is_exec, int opaque, unsigned size) @@ -764,14 +766,14 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, { CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu); - if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { - cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); + if (!cpu->ignore_memory_transaction_failures && + cc->tcg_ops.do_transaction_failed) { + cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, + access_type, mmu_idx, attrs, + response, retaddr); } } -#endif - /** * cpu_set_pc: * @cpu: The CPU to set the program counter for. diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index da27faae..75b76609 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -1510,7 +1510,7 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data CPUClass *cc = CPU_CLASS(uc, oc); #ifndef CONFIG_USER_ONLY - cc->do_interrupt = arm_v7m_cpu_do_interrupt; + cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt; #endif cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; @@ -2115,11 +2115,11 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data cc->debug_check_watchpoint = arm_debug_check_watchpoint; cc->do_unaligned_access = arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) - cc->do_transaction_failed = arm_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt; #endif -#endif +#endif /* CONFIG_TCG */ } void arm_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info) diff --git a/qemu/target/m68k/cpu.c b/qemu/target/m68k/cpu.c index 40f84241..92fd04fa 100644 --- a/qemu/target/m68k/cpu.c +++ b/qemu/target/m68k/cpu.c @@ -270,7 +270,7 @@ static void m68k_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->set_pc = m68k_cpu_set_pc; cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) - cc->do_transaction_failed = m68k_cpu_transaction_failed; + cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; #endif cc->tcg_ops.initialize = m68k_tcg_init; diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c index 8716222c..60a4d3ea 100644 --- a/qemu/target/mips/cpu.c +++ b/qemu/target/mips/cpu.c @@ -175,7 +175,6 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->has_work = mips_cpu_has_work; cc->set_pc = mips_cpu_set_pc; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = mips_cpu_do_transaction_failed; cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; #endif @@ -185,6 +184,9 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed; +#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ } diff --git a/qemu/target/sparc/cpu.c b/qemu/target/sparc/cpu.c index 7cd14fda..80941418 100644 --- a/qemu/target/sparc/cpu.c +++ b/qemu/target/sparc/cpu.c @@ -850,7 +850,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = sparc_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; // Unicorn: commented out