diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h
index 40f76aa1..31ba2499 100644
--- a/include/unicorn/arm64.h
+++ b/include/unicorn/arm64.h
@@ -290,6 +290,12 @@ typedef enum uc_arm64_reg {
     UC_ARM64_REG_TPIDR_EL0,
     UC_ARM64_REG_TPIDRRO_EL0,
     UC_ARM64_REG_TPIDR_EL1,
+
+    UC_ARM64_REG_PSTATE,        // PSTATE pseudoregister
+
+    //> floating point control and status registers
+    UC_ARM64_REG_FPCR,
+    UC_ARM64_REG_FPSR,
     
     UC_ARM64_REG_ENDING,		// <-- mark the end of the list of registers
 
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 45ce2b37..0e92a378 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -106,6 +106,15 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
                 case UC_ARM64_REG_NZCV:
                     *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
                     break;
+                case UC_ARM64_REG_PSTATE:
+                    *(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env);
+                    break;
+                case UC_ARM64_REG_FPCR:
+                    *(uint32_t *)value = vfp_get_fpcr(&ARM_CPU(uc, mycpu)->env);
+                    break;
+                case UC_ARM64_REG_FPSR:
+                    *(uint32_t *)value = vfp_get_fpsr(&ARM_CPU(uc, mycpu)->env);
+                    break;
             }
         }
     }
@@ -174,6 +183,15 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
                 case UC_ARM64_REG_NZCV:
                     cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
                     break;
+                case UC_ARM64_REG_PSTATE:
+                    pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
+                    break;
+                case UC_ARM64_REG_FPCR:
+                    vfp_set_fpcr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
+                    break;
+                case UC_ARM64_REG_FPSR:
+                    vfp_set_fpsr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
+                    break;
             }
         }
     }