From eec3a5f84374cb662183067cfaf17815ffe1a15a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 24 Feb 2018 19:04:24 -0500 Subject: [PATCH] target-arm: Define new arm_is_el3_or_mon() function The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Backports commit 712058764da29b2908f6fbf56760ca4f15980709 from qemu --- qemu/target-arm/cpu.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index 1fc8fb93..c7f666cc 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -1145,8 +1145,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) } } -/* Return true if the processor is in secure state */ -static inline bool arm_is_secure(CPUARMState *env) +/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ +static inline bool arm_is_el3_or_mon(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { @@ -1158,6 +1158,15 @@ static inline bool arm_is_secure(CPUARMState *env) return true; } } + return false; +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ + if (arm_is_el3_or_mon(env)) { + return true; + } return arm_is_secure_below_el3(env); }