From eeefc3c4a2e475df92eebdaefee51669bf39387c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= Date: Thu, 4 Mar 2021 14:26:20 -0500 Subject: [PATCH] target/arm: generalize 2-stage page-walk condition The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Backports 7879460a6149ed5e80c29cac85449191d9c5754a --- qemu/target/arm/helper.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 14f62dcc..0899caff 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -11880,12 +11880,12 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_E10_0 || - mmu_idx == ARMMMUIdx_E10_1 || - mmu_idx == ARMMMUIdx_E10_1_PAN) { + ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + + if (mmu_idx != s1_mmu_idx) { /* * Call ourselves recursively to do the stage 1 and then stage 2 - * translations. + * translations if mmu_idx is a two-stage regime. */ if (arm_feature(env, ARM_FEATURE_EL2)) { hwaddr ipa; @@ -11893,9 +11893,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, int ret; ARMCacheAttrs cacheattrs2 = {0}; - ret = get_phys_addr(env, address, access_type, - stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fi, cacheattrs); + ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, + attrs, prot, page_size, fi, cacheattrs); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {