diff --git a/qemu/aarch64.h b/qemu/aarch64.h index f5ceefeb..5b19de41 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64 #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64 #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64 #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64 #define tcg_gen_st_vec tcg_gen_st_vec_aarch64 @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 54147397..9a747b0f 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb +#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb +#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb +#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64eb +#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64eb #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb #define tcg_gen_st_vec tcg_gen_st_vec_aarch64eb @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb #define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb +#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64eb +#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64eb +#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64eb +#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64eb #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64eb #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 074f4fdb..0c2e5407 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_arm #define tcg_gen_shri_i64 tcg_gen_shri_i64_arm #define tcg_gen_shri_vec tcg_gen_shri_vec_arm +#define tcg_gen_smax_i32 tcg_gen_smax_i32_arm +#define tcg_gen_smax_i64 tcg_gen_smax_i64_arm +#define tcg_gen_smin_i32 tcg_gen_smin_i32_arm +#define tcg_gen_smin_i64 tcg_gen_smin_i64_arm #define tcg_gen_st_i32 tcg_gen_st_i32_arm #define tcg_gen_st_i64 tcg_gen_st_i64_arm #define tcg_gen_st_vec tcg_gen_st_vec_arm @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm #define tcg_gen_subi_i32 tcg_gen_subi_i32_arm #define tcg_gen_subi_i64 tcg_gen_subi_i64_arm +#define tcg_gen_umax_i32 tcg_gen_umax_i32_arm +#define tcg_gen_umax_i64 tcg_gen_umax_i64_arm +#define tcg_gen_umin_i32 tcg_gen_umin_i32_arm +#define tcg_gen_umin_i64 tcg_gen_umin_i64_arm #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_arm #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index f3b64030..47210de3 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb #define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb #define tcg_gen_shri_vec tcg_gen_shri_vec_armeb +#define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb +#define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb +#define tcg_gen_smin_i32 tcg_gen_smin_i32_armeb +#define tcg_gen_smin_i64 tcg_gen_smin_i64_armeb #define tcg_gen_st_i32 tcg_gen_st_i32_armeb #define tcg_gen_st_i64 tcg_gen_st_i64_armeb #define tcg_gen_st_vec tcg_gen_st_vec_armeb @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb #define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb #define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb +#define tcg_gen_umax_i32 tcg_gen_umax_i32_armeb +#define tcg_gen_umax_i64 tcg_gen_umax_i64_armeb +#define tcg_gen_umin_i32 tcg_gen_umin_i32_armeb +#define tcg_gen_umin_i64 tcg_gen_umin_i64_armeb #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_armeb #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 97b4d932..f016fb91 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2766,6 +2766,10 @@ symbols = ( 'tcg_gen_shri_i32', 'tcg_gen_shri_i64', 'tcg_gen_shri_vec', + 'tcg_gen_smax_i32', + 'tcg_gen_smax_i64', + 'tcg_gen_smin_i32', + 'tcg_gen_smin_i64', 'tcg_gen_st_i32', 'tcg_gen_st_i64', 'tcg_gen_st_vec', @@ -2779,6 +2783,10 @@ symbols = ( 'tcg_gen_subfi_i64', 'tcg_gen_subi_i32', 'tcg_gen_subi_i64', + 'tcg_gen_umax_i32', + 'tcg_gen_umax_i64', + 'tcg_gen_umin_i32', + 'tcg_gen_umin_i64', 'tcg_gen_vec_add8_i64', 'tcg_gen_vec_add16_i64', 'tcg_gen_vec_add32_i64', diff --git a/qemu/m68k.h b/qemu/m68k.h index 8363f966..9a36692d 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k #define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k #define tcg_gen_shri_vec tcg_gen_shri_vec_m68k +#define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k +#define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k +#define tcg_gen_smin_i32 tcg_gen_smin_i32_m68k +#define tcg_gen_smin_i64 tcg_gen_smin_i64_m68k #define tcg_gen_st_i32 tcg_gen_st_i32_m68k #define tcg_gen_st_i64 tcg_gen_st_i64_m68k #define tcg_gen_st_vec tcg_gen_st_vec_m68k @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k #define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k #define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k +#define tcg_gen_umax_i32 tcg_gen_umax_i32_m68k +#define tcg_gen_umax_i64 tcg_gen_umax_i64_m68k +#define tcg_gen_umin_i32 tcg_gen_umin_i32_m68k +#define tcg_gen_umin_i64 tcg_gen_umin_i64_m68k #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_m68k #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 1d368131..d56fd95d 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips #define tcg_gen_shri_vec tcg_gen_shri_vec_mips +#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips +#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips +#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips +#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips #define tcg_gen_st_i32 tcg_gen_st_i32_mips #define tcg_gen_st_i64 tcg_gen_st_i64_mips #define tcg_gen_st_vec tcg_gen_st_vec_mips @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips +#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips +#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips +#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips +#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 5a53b0d0..bda90517 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64 #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64 #define tcg_gen_st_i32 tcg_gen_st_i32_mips64 #define tcg_gen_st_i64 tcg_gen_st_i64_mips64 #define tcg_gen_st_vec tcg_gen_st_vec_mips64 @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index e0547081..72ded0de 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el +#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el +#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el +#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64el +#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64el #define tcg_gen_st_i32 tcg_gen_st_i32_mips64el #define tcg_gen_st_i64 tcg_gen_st_i64_mips64el #define tcg_gen_st_vec tcg_gen_st_vec_mips64el @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el +#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64el +#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64el +#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64el +#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64el #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64el #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 0b24b8d3..a53af4f9 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel #define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel #define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel +#define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel +#define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel +#define tcg_gen_smin_i32 tcg_gen_smin_i32_mipsel +#define tcg_gen_smin_i64 tcg_gen_smin_i64_mipsel #define tcg_gen_st_i32 tcg_gen_st_i32_mipsel #define tcg_gen_st_i64 tcg_gen_st_i64_mipsel #define tcg_gen_st_vec tcg_gen_st_vec_mipsel @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel #define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel #define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel +#define tcg_gen_umax_i32 tcg_gen_umax_i32_mipsel +#define tcg_gen_umax_i64 tcg_gen_umax_i64_mipsel +#define tcg_gen_umin_i32 tcg_gen_umin_i32_mipsel +#define tcg_gen_umin_i64 tcg_gen_umin_i64_mipsel #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mipsel #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index ff11ce00..85c913d1 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc #define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc #define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc +#define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc +#define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc +#define tcg_gen_smin_i32 tcg_gen_smin_i32_powerpc +#define tcg_gen_smin_i64 tcg_gen_smin_i64_powerpc #define tcg_gen_st_i32 tcg_gen_st_i32_powerpc #define tcg_gen_st_i64 tcg_gen_st_i64_powerpc #define tcg_gen_st_vec tcg_gen_st_vec_powerpc @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc #define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc #define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc +#define tcg_gen_umax_i32 tcg_gen_umax_i32_powerpc +#define tcg_gen_umax_i64 tcg_gen_umax_i64_powerpc +#define tcg_gen_umin_i32 tcg_gen_umin_i32_powerpc +#define tcg_gen_umin_i64 tcg_gen_umin_i64_powerpc #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_powerpc #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_powerpc diff --git a/qemu/sparc.h b/qemu/sparc.h index 289f5077..62ff5d00 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc +#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc +#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc +#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc +#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc #define tcg_gen_st_i32 tcg_gen_st_i32_sparc #define tcg_gen_st_i64 tcg_gen_st_i64_sparc #define tcg_gen_st_vec tcg_gen_st_vec_sparc @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc #define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc +#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc +#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc +#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc +#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index e18d1140..ca99d380 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64 #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc64 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc64 #define tcg_gen_st_i32 tcg_gen_st_i32_sparc64 #define tcg_gen_st_i64 tcg_gen_st_i64_sparc64 #define tcg_gen_st_vec tcg_gen_st_vec_sparc64 @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc64 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc64 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc64 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc64 diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c index 4c5f9d13..7701aaa9 100644 --- a/qemu/tcg/tcg-op.c +++ b/qemu/tcg/tcg-op.c @@ -1040,6 +1040,26 @@ void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) } } +void tcg_gen_smin_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(s, TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(s, TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(s, TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(s, TCG_COND_LTU, ret, a, b, b, a); +} + /* 64-bit ops */ #if TCG_TARGET_REG_BITS == 32 @@ -2452,6 +2472,26 @@ void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, tcg_temp_free_i64(s, t2); } +void tcg_gen_smin_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(s, TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(s, TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(s, TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(s, TCG_COND_LTU, ret, a, b, b, a); +} + /* Size changing operations. */ void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg) diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index f91f6f5e..9b501b54 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -337,6 +337,10 @@ void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_smin_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_smax_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umin_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umax_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); static inline void tcg_gen_discard_i32(TCGContext *s, TCGv_i32 arg) { @@ -522,6 +526,11 @@ void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_smin_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_smax_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umin_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umax_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); + #if TCG_TARGET_REG_BITS == 64 static inline void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg) @@ -1033,6 +1042,10 @@ void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCG #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 +#define tcg_gen_smin_tl tcg_gen_smin_i64 +#define tcg_gen_umin_tl tcg_gen_umin_i64 +#define tcg_gen_smax_tl tcg_gen_smax_i64 +#define tcg_gen_umax_tl tcg_gen_umax_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 @@ -1131,6 +1144,10 @@ void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCG #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 +#define tcg_gen_smin_tl tcg_gen_smin_i32 +#define tcg_gen_umin_tl tcg_gen_umin_i32 +#define tcg_gen_smax_tl tcg_gen_smax_i32 +#define tcg_gen_umax_tl tcg_gen_umax_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 diff --git a/qemu/x86_64.h b/qemu/x86_64.h index af7ddeb9..6a3fc2e1 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2760,6 +2760,10 @@ #define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64 #define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_x86_64 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_x86_64 #define tcg_gen_st_i32 tcg_gen_st_i32_x86_64 #define tcg_gen_st_i64 tcg_gen_st_i64_x86_64 #define tcg_gen_st_vec tcg_gen_st_vec_x86_64 @@ -2773,6 +2777,10 @@ #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_x86_64 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_x86_64 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_x86_64 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_x86_64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_x86_64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_x86_64