From f10de71e73510e67e14d58583432634e44f7d906 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Sat, 21 Mar 2020 12:30:42 -0400 Subject: [PATCH] target/mips: Amend CP0 WatchHi register implementation WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/ DMFC0 in 64-bit architectures. Backports commit feafe82cc2289a31b3e3f11dc76f3539ea22d670 from qemu --- qemu/header_gen.py | 3 +++ qemu/mips.h | 3 +++ qemu/mips64.h | 3 +++ qemu/mips64el.h | 3 +++ qemu/mipsel.h | 3 +++ qemu/target/mips/cpu.h | 2 +- qemu/target/mips/helper.h | 3 +++ qemu/target/mips/op_helper.c | 23 ++++++++++++++++++-- qemu/target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++++- 9 files changed, 81 insertions(+), 4 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 60f484bd..f56e56e1 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -4711,6 +4711,7 @@ mips_symbols = ( 'helper_dmfc0_tcrestart', 'helper_dmfc0_tcschedule', 'helper_dmfc0_tcschefback', + 'helper_dmfc0_watchhi', 'helper_dmfc0_watchlo', 'helper_dmsub', 'helper_dmsubu', @@ -4919,6 +4920,7 @@ mips_symbols = ( 'helper_mfc0_watchlo', 'helper_mfhc0_maar', 'helper_mfhc0_saar', + 'helper_mfhc0_watchhi', 'helper_mftacx', 'helper_mftc0_cause', 'helper_mftc0_configx', @@ -5190,6 +5192,7 @@ mips_symbols = ( 'helper_mtc0_yqmask', 'helper_mthc0_maar', 'helper_mthc0_saar', + 'helper_mthc0_watchhi', 'helper_mthlip', 'helper_mttacx', 'helper_mttc0_cause', diff --git a/qemu/mips.h b/qemu/mips.h index 435f0c83..e93dee21 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3597,6 +3597,7 @@ #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips #define helper_dmfc0_tcschedule helper_dmfc0_tcschedule_mips #define helper_dmfc0_tcschefback helper_dmfc0_tcschefback_mips +#define helper_dmfc0_watchhi helper_dmfc0_watchhi_mips #define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips #define helper_dmsub helper_dmsub_mips #define helper_dmsubu helper_dmsubu_mips @@ -3805,6 +3806,7 @@ #define helper_mfc0_watchlo helper_mfc0_watchlo_mips #define helper_mfhc0_maar helper_mfhc0_maar_mips #define helper_mfhc0_saar helper_mfhc0_saar_mips +#define helper_mfhc0_watchhi helper_mfhc0_watchhi_mips #define helper_mftacx helper_mftacx_mips #define helper_mftc0_cause helper_mftc0_cause_mips #define helper_mftc0_configx helper_mftc0_configx_mips @@ -4076,6 +4078,7 @@ #define helper_mtc0_yqmask helper_mtc0_yqmask_mips #define helper_mthc0_maar helper_mthc0_maar_mips #define helper_mthc0_saar helper_mthc0_saar_mips +#define helper_mthc0_watchhi helper_mthc0_watchhi_mips #define helper_mthlip helper_mthlip_mips #define helper_mttacx helper_mttacx_mips #define helper_mttc0_cause helper_mttc0_cause_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 282228f1..32eb5854 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3597,6 +3597,7 @@ #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips64 #define helper_dmfc0_tcschedule helper_dmfc0_tcschedule_mips64 #define helper_dmfc0_tcschefback helper_dmfc0_tcschefback_mips64 +#define helper_dmfc0_watchhi helper_dmfc0_watchhi_mips64 #define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips64 #define helper_dmsub helper_dmsub_mips64 #define helper_dmsubu helper_dmsubu_mips64 @@ -3805,6 +3806,7 @@ #define helper_mfc0_watchlo helper_mfc0_watchlo_mips64 #define helper_mfhc0_maar helper_mfhc0_maar_mips64 #define helper_mfhc0_saar helper_mfhc0_saar_mips64 +#define helper_mfhc0_watchhi helper_mfhc0_watchhi_mips64 #define helper_mftacx helper_mftacx_mips64 #define helper_mftc0_cause helper_mftc0_cause_mips64 #define helper_mftc0_configx helper_mftc0_configx_mips64 @@ -4076,6 +4078,7 @@ #define helper_mtc0_yqmask helper_mtc0_yqmask_mips64 #define helper_mthc0_maar helper_mthc0_maar_mips64 #define helper_mthc0_saar helper_mthc0_saar_mips64 +#define helper_mthc0_watchhi helper_mthc0_watchhi_mips64 #define helper_mthlip helper_mthlip_mips64 #define helper_mttacx helper_mttacx_mips64 #define helper_mttc0_cause helper_mttc0_cause_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index f0f08b3e..2e2674cf 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3597,6 +3597,7 @@ #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mips64el #define helper_dmfc0_tcschedule helper_dmfc0_tcschedule_mips64el #define helper_dmfc0_tcschefback helper_dmfc0_tcschefback_mips64el +#define helper_dmfc0_watchhi helper_dmfc0_watchhi_mips64el #define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips64el #define helper_dmsub helper_dmsub_mips64el #define helper_dmsubu helper_dmsubu_mips64el @@ -3805,6 +3806,7 @@ #define helper_mfc0_watchlo helper_mfc0_watchlo_mips64el #define helper_mfhc0_maar helper_mfhc0_maar_mips64el #define helper_mfhc0_saar helper_mfhc0_saar_mips64el +#define helper_mfhc0_watchhi helper_mfhc0_watchhi_mips64el #define helper_mftacx helper_mftacx_mips64el #define helper_mftc0_cause helper_mftc0_cause_mips64el #define helper_mftc0_configx helper_mftc0_configx_mips64el @@ -4076,6 +4078,7 @@ #define helper_mtc0_yqmask helper_mtc0_yqmask_mips64el #define helper_mthc0_maar helper_mthc0_maar_mips64el #define helper_mthc0_saar helper_mthc0_saar_mips64el +#define helper_mthc0_watchhi helper_mthc0_watchhi_mips64el #define helper_mthlip helper_mthlip_mips64el #define helper_mttacx helper_mttacx_mips64el #define helper_mttc0_cause helper_mttc0_cause_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index b69aec56..ea8abc38 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3597,6 +3597,7 @@ #define helper_dmfc0_tcrestart helper_dmfc0_tcrestart_mipsel #define helper_dmfc0_tcschedule helper_dmfc0_tcschedule_mipsel #define helper_dmfc0_tcschefback helper_dmfc0_tcschefback_mipsel +#define helper_dmfc0_watchhi helper_dmfc0_watchhi_mipsel #define helper_dmfc0_watchlo helper_dmfc0_watchlo_mipsel #define helper_dmsub helper_dmsub_mipsel #define helper_dmsubu helper_dmsubu_mipsel @@ -3805,6 +3806,7 @@ #define helper_mfc0_watchlo helper_mfc0_watchlo_mipsel #define helper_mfhc0_maar helper_mfhc0_maar_mipsel #define helper_mfhc0_saar helper_mfhc0_saar_mipsel +#define helper_mfhc0_watchhi helper_mfhc0_watchhi_mipsel #define helper_mftacx helper_mftacx_mipsel #define helper_mftc0_cause helper_mftc0_cause_mipsel #define helper_mftc0_configx helper_mftc0_configx_mipsel @@ -4076,6 +4078,7 @@ #define helper_mtc0_yqmask helper_mtc0_yqmask_mipsel #define helper_mthc0_maar helper_mthc0_maar_mipsel #define helper_mthc0_saar helper_mthc0_saar_mipsel +#define helper_mthc0_watchhi helper_mthc0_watchhi_mipsel #define helper_mthlip helper_mthlip_mipsel #define helper_mttacx helper_mttacx_mipsel #define helper_mttc0_cause helper_mttc0_cause_mipsel diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h index 72f79d58..18b48fb2 100644 --- a/qemu/target/mips/cpu.h +++ b/qemu/target/mips/cpu.h @@ -959,7 +959,7 @@ struct CPUMIPSState { /* * CP0 Register 19 */ - int32_t CP0_WatchHi[8]; + uint64_t CP0_WatchHi[8]; #define CP0WH_ASID 16 /* * CP0 Register 20 diff --git a/qemu/target/mips/helper.h b/qemu/target/mips/helper.h index 83ac0765..1d272592 100644 --- a/qemu/target/mips/helper.h +++ b/qemu/target/mips/helper.h @@ -76,6 +76,7 @@ DEF_HELPER_1(mfc0_maar, tl, env) DEF_HELPER_1(mfhc0_maar, tl, env) DEF_HELPER_2(mfc0_watchlo, tl, env, i32) DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) DEF_HELPER_1(mfc0_debug, tl, env) DEF_HELPER_1(mftc0_debug, tl, env) #ifdef TARGET_MIPS64 @@ -87,6 +88,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ @@ -157,6 +159,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl) DEF_HELPER_2(mtc0_maari, void, env, tl) DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) DEF_HELPER_2(mtc0_xcontext, void, env, tl) DEF_HELPER_2(mtc0_framemask, void, env, tl) DEF_HELPER_2(mtc0_debug, void, env, tl) diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c index 1404c784..8164a6b1 100644 --- a/qemu/target/mips/op_helper.c +++ b/qemu/target/mips/op_helper.c @@ -975,7 +975,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) { - return env->CP0_WatchHi[sel]; + return (int32_t) env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel] >> 32; } target_ulong helper_mfc0_debug(CPUMIPSState *env) @@ -1044,6 +1049,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) return env->CP0_WatchLo[sel]; } +target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} + target_ulong helper_dmfc0_saar(CPUMIPSState *env) { if ((env->CP0_SAARI & 0x3f) < 2) { @@ -1860,11 +1870,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { - int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + if ((env->CP0_Config5 >> CP0C5_MI) & 1) { + mask |= 0xFFFFFFFF00000000ULL; /* MMID */ + } env->CP0_WatchHi[sel] = arg1 & mask; env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) +{ + env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); +} + void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) { target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 9b3b61d9..7c7224c9 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -2516,6 +2516,7 @@ typedef struct DisasContext { bool nan2008; bool abs2008; bool saar; + bool mi; // Unicorn engine struct uc_struct *uc; @@ -6763,6 +6764,25 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; + case CP0_REGISTER_19: + switch (sel) { + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: + /* upper 32 bits are only available when Config5MI != 0 */ + CP0_CHECK(ctx->mi); + gen_mfhc0_load64(ctx, arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); + register_name = "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case CP0_REGISTER_28: switch (sel) { case CP0_REG28__TAGLO: @@ -6851,6 +6871,25 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } break; + case CP0_REGISTER_19: + switch (sel) { + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: + /* upper 32 bits are only available when Config5MI != 0 */ + CP0_CHECK(ctx->mi); + gen_helper_0e1i(s, mthc0_watchhi, arg, sel); + register_name = "WatchHi"; + break; + default: + goto cp0_unimplemented; + } + break; case CP0_REGISTER_28: switch (sel) { case CP0_REG28__TAGLO: @@ -8894,7 +8933,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case CP0_REG19__WATCHHI6: case CP0_REG19__WATCHHI7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); - gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel); + gen_helper_1e0i(tcg_ctx, dmfc0_watchhi, arg, sel); register_name = "WatchHi"; break; default: @@ -30186,6 +30225,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx = MIPS_HFLAG_UM;