From f120ad5308400b5c1e71dc42240d6499014feff3 Mon Sep 17 00:00:00 2001 From: Fabian Aggeler Date: Sun, 11 Feb 2018 18:50:51 -0500 Subject: [PATCH] target-arm: implement IRQ/FIQ routing to Monitor mode SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu --- qemu/target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 1bbfd2c0..8f3259b2 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -3743,6 +3743,11 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; @@ -3750,6 +3755,10 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; offset = 4; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } break; case EXCP_SMC: new_mode = ARM_CPU_MODE_MON;