From f14ece4aa1ac3484a27b81f9128fb358bd4be967 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9=20Draszik?= <git@andred.net>
Date: Mon, 26 Feb 2018 03:50:16 -0500
Subject: [PATCH] target-mips: add 24KEc CPU definition

Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).

Backports commit e9deaad8a58c899dc32e9fdeff9e533070e79dca from qemu
---
 qemu/target-mips/translate_init.c | 38 +++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c
index 5320b02a..94ca3b59 100644
--- a/qemu/target-mips/translate_init.c
+++ b/qemu/target-mips/translate_init.c
@@ -334,6 +334,44 @@ static const mips_def_t mips_defs[] =
         CPU_MIPS32R2 | ASE_MIPS16,
         MMU_TYPE_R4000,
     },
+    {
+        "24KEc",
+        0x00019600,
+        MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_CA),
+        MIPS_CONFIG2,
+        MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
+        0,0,
+        0,0,
+        0,
+        0,
+        0,
+        4,
+        32,
+        2,
+        /* we have a DSP, but no FPU */
+        0x1378FF1F,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        32,
+        32,
+        0,0,
+        0,0,
+        0,0,
+        0,0,
+        0,0,
+        0,0,
+        CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+        MMU_TYPE_R4000,
+    },
     {
         "24Kf",
         0x00019300,