From f1f3ff39eb43f79f80cfe5fa72b90c1d340dfcd2 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 18 Feb 2018 22:18:26 -0500 Subject: [PATCH] target-arm: Support multiple address spaces in page table walks If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Backports commit 5ce4ff6502fc6ae01a30c3917996c6c41be1d176 from qemu --- qemu/target-arm/cpu.h | 9 +++++++++ qemu/target-arm/helper.c | 8 ++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index a6673874..fbd506cd 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -2051,6 +2051,15 @@ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) { return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; } + +/* Return the AddressSpace to use for a memory access + * (which depends on whether the access is S or NS, and whether + * the board gave us a separate AddressSpace for S accesses). + */ +static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) +{ + return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); +} #endif #endif diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 59804b1f..a7679e3a 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -5617,13 +5617,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs->uc, cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {0}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldl(cs->as, addr, attrs, NULL); + return address_space_ldl(as, addr, attrs, NULL); } static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, @@ -5633,13 +5635,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs->uc, cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {0}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldq(cs->as, addr, attrs, NULL); + return address_space_ldq(as, addr, attrs, NULL); } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,