From f28514178a084756e4487ea5dcb8b3624c72a14c Mon Sep 17 00:00:00 2001 From: Julia Suvorova Date: Fri, 29 Jun 2018 14:15:31 -0500 Subject: [PATCH] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally aligned memory accesses for load/store instructions. Backports commit 2aeba0d007d33efa12a6339bb140aa634e0d52eb from qemu --- qemu/target/arm/translate.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 1df5f3c7..3fb1c973 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -1137,7 +1137,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + opc |= MO_ALIGN; + } + + addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(s->uc, val, addr, index, opc); tcg_temp_free(tcg_ctx, addr); } @@ -1146,7 +1153,14 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, TCGMemOp opc) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv addr; + + if (arm_dc_feature(s, ARM_FEATURE_M) && + !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + opc |= MO_ALIGN; + } + + addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(s->uc, val, addr, index, opc); tcg_temp_free(tcg_ctx, addr); }