From f2d68a40791909cc978b373cc6c57518ceadea84 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Tue, 3 Jul 2018 00:59:44 -0400 Subject: [PATCH] target/mips: Update gen_flt_ldst() Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Backports commit b52d3bfa2d54d99ef25f6d008815eecc53b67bfe from qemu --- qemu/target/mips/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 16135b35..bb182666 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -2449,12 +2449,10 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, - int base, int16_t offset) + TCGv t0) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv t0 = tcg_temp_new(tcg_ctx); - gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) { @@ -2497,15 +2495,16 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, default: MIPS_INVAL("flt_ldst"); generate_exception_end(ctx, EXCP_RI); - goto out; + break; } - out: - tcg_temp_free(tcg_ctx, t0); } static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, int rs, int16_t imm) { + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0 = tcg_temp_new(tcg_ctx); + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); switch (op) { @@ -2514,11 +2513,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, check_insn(ctx, ISA_MIPS2); /* Fallthrough */ default: - gen_flt_ldst(ctx, op, rt, rs, imm); + gen_base_offset_addr(ctx, t0, rs, imm); + gen_flt_ldst(ctx, op, rt, t0); } } else { generate_exception_err(ctx, EXCP_CpU, 1); } + tcg_temp_free(tcg_ctx, t0); } /* Arithmetic with immediate operand */