diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 30dab47e..31ef43b7 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_aarch64
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_aarch64
 #define helper_gvec_rotl8i helper_gvec_rotl8i_aarch64
 #define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64
 #define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index c045d175..0f7e6ece 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64eb
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64eb
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64eb
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_aarch64eb
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_aarch64eb
 #define helper_gvec_rotl8i helper_gvec_rotl8i_aarch64eb
 #define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64eb
 #define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64eb
diff --git a/qemu/arm.h b/qemu/arm.h
index bf390138..bcc57e9b 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_arm
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_arm
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_arm
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_arm
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_arm
 #define helper_gvec_rotl8i helper_gvec_rotl8i_arm
 #define helper_gvec_rotl16i helper_gvec_rotl16i_arm
 #define helper_gvec_rotl32i helper_gvec_rotl32i_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index e4f868da..e4a5754d 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_armeb
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_armeb
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_armeb
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_armeb
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_armeb
 #define helper_gvec_rotl8i helper_gvec_rotl8i_armeb
 #define helper_gvec_rotl16i helper_gvec_rotl16i_armeb
 #define helper_gvec_rotl32i helper_gvec_rotl32i_armeb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 17f6abbb..d1110965 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -1385,6 +1385,8 @@ symbols = (
     'helper_gvec_qrdmlah_s32',
     'helper_gvec_qrdmlsh_s16',
     'helper_gvec_qrdmlsh_s32',
+    'helper_gvec_recps_nf_h',
+    'helper_gvec_recps_nf_s',
     'helper_gvec_rotl8i',
     'helper_gvec_rotl16i',
     'helper_gvec_rotl32i',
diff --git a/qemu/m68k.h b/qemu/m68k.h
index ca6b3cdf..c44a708c 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_m68k
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_m68k
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_m68k
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_m68k
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_m68k
 #define helper_gvec_rotl8i helper_gvec_rotl8i_m68k
 #define helper_gvec_rotl16i helper_gvec_rotl16i_m68k
 #define helper_gvec_rotl32i helper_gvec_rotl32i_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index f81b6c2e..3926bf7d 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_mips
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_mips
 #define helper_gvec_rotl8i helper_gvec_rotl8i_mips
 #define helper_gvec_rotl16i helper_gvec_rotl16i_mips
 #define helper_gvec_rotl32i helper_gvec_rotl32i_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index 02e7ebed..bc281af2 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_mips64
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_mips64
 #define helper_gvec_rotl8i helper_gvec_rotl8i_mips64
 #define helper_gvec_rotl16i helper_gvec_rotl16i_mips64
 #define helper_gvec_rotl32i helper_gvec_rotl32i_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 4a3d7ac1..733d6012 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64el
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64el
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64el
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_mips64el
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_mips64el
 #define helper_gvec_rotl8i helper_gvec_rotl8i_mips64el
 #define helper_gvec_rotl16i helper_gvec_rotl16i_mips64el
 #define helper_gvec_rotl32i helper_gvec_rotl32i_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index e182bf40..cbdb0473 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mipsel
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mipsel
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mipsel
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_mipsel
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_mipsel
 #define helper_gvec_rotl8i helper_gvec_rotl8i_mipsel
 #define helper_gvec_rotl16i helper_gvec_rotl16i_mipsel
 #define helper_gvec_rotl32i helper_gvec_rotl32i_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index 194243b2..e169008b 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_powerpc
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_powerpc
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_powerpc
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_powerpc
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_powerpc
 #define helper_gvec_rotl8i helper_gvec_rotl8i_powerpc
 #define helper_gvec_rotl16i helper_gvec_rotl16i_powerpc
 #define helper_gvec_rotl32i helper_gvec_rotl32i_powerpc
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index b1e05a7d..20acba33 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv32
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv32
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv32
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_riscv32
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_riscv32
 #define helper_gvec_rotl8i helper_gvec_rotl8i_riscv32
 #define helper_gvec_rotl16i helper_gvec_rotl16i_riscv32
 #define helper_gvec_rotl32i helper_gvec_rotl32i_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 7aa969b5..e9bf5ffd 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv64
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv64
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_riscv64
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_riscv64
 #define helper_gvec_rotl8i helper_gvec_rotl8i_riscv64
 #define helper_gvec_rotl16i helper_gvec_rotl16i_riscv64
 #define helper_gvec_rotl32i helper_gvec_rotl32i_riscv64
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 94e0bb74..0d9ec264 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_sparc
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_sparc
 #define helper_gvec_rotl8i helper_gvec_rotl8i_sparc
 #define helper_gvec_rotl16i helper_gvec_rotl16i_sparc
 #define helper_gvec_rotl32i helper_gvec_rotl32i_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index ac0960fd..609cf27d 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc64
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc64
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_sparc64
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_sparc64
 #define helper_gvec_rotl8i helper_gvec_rotl8i_sparc64
 #define helper_gvec_rotl16i helper_gvec_rotl16i_sparc64
 #define helper_gvec_rotl32i helper_gvec_rotl32i_sparc64
diff --git a/qemu/target/arm/helper.h b/qemu/target/arm/helper.h
index e12a7904..88032cbe 100644
--- a/qemu/target/arm/helper.h
+++ b/qemu/target/arm/helper.h
@@ -223,7 +223,6 @@ DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
 DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
 DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr)
 
-DEF_HELPER_3(recps_f32, f32, env, f32, f32)
 DEF_HELPER_3(rsqrts_f32, f32, env, f32, f32)
 DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
 DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
@@ -672,6 +671,9 @@ DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i3
 DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
 
diff --git a/qemu/target/arm/translate-neon.inc.c b/qemu/target/arm/translate-neon.inc.c
index f7a7c501..22e3289e 100644
--- a/qemu/target/arm/translate-neon.inc.c
+++ b/qemu/target/arm/translate-neon.inc.c
@@ -1092,6 +1092,7 @@ DO_3S_FP_GVEC(VMLA, gen_helper_gvec_fmla_s, gen_helper_gvec_fmla_h)
 DO_3S_FP_GVEC(VMLS, gen_helper_gvec_fmls_s, gen_helper_gvec_fmls_h)
 DO_3S_FP_GVEC(VFMA, gen_helper_gvec_vfma_s, gen_helper_gvec_vfma_h)
 DO_3S_FP_GVEC(VFMS, gen_helper_gvec_vfms_s, gen_helper_gvec_vfms_h)
+DO_3S_FP_GVEC(VRECPS, gen_helper_gvec_recps_nf_s, gen_helper_gvec_recps_nf_h)
 
 WRAP_FP_GVEC(gen_VMAXNM_fp32_3s, FPST_STD, gen_helper_gvec_fmaxnum_s)
 WRAP_FP_GVEC(gen_VMAXNM_fp16_3s, FPST_STD_F16, gen_helper_gvec_fmaxnum_h)
@@ -1130,26 +1131,6 @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
     return do_3same(s, a, gen_VMINNM_fp32_3s);
 }
 
-WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32)
-
-static void gen_VRECPS_fp_3s(TCGContext *s, unsigned vece, uint32_t rd_ofs,
-                             uint32_t rn_ofs, uint32_t rm_ofs,
-                             uint32_t oprsz, uint32_t maxsz)
-{
-    static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp };
-    tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);
-}
-
-static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a)
-{
-    if (a->size != 0) {
-        /* TODO fp16 support */
-        return false;
-    }
-
-    return do_3same(s, a, gen_VRECPS_fp_3s);
-}
-
 WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32)
 
 static void gen_VRSQRTS_fp_3s(TCGContext *s, unsigned vece, uint32_t rd_ofs,
diff --git a/qemu/target/arm/vec_helper.c b/qemu/target/arm/vec_helper.c
index 8351cbcc..def56e87 100644
--- a/qemu/target/arm/vec_helper.c
+++ b/qemu/target/arm/vec_helper.c
@@ -798,6 +798,34 @@ static float32 float32_abd(float32 op1, float32 op2, float_status *stat)
     return float32_abs(float32_sub(op1, op2, stat));
 }
 
+/*
+ * Reciprocal step. These are the AArch32 version which uses a
+ * non-fused multiply-and-subtract.
+ */
+static float16 float16_recps_nf(float16 op1, float16 op2, float_status *stat)
+{
+    op1 = float16_squash_input_denormal(op1, stat);
+    op2 = float16_squash_input_denormal(op2, stat);
+
+    if ((float16_is_infinity(op1) && float16_is_zero(op2)) ||
+        (float16_is_infinity(op2) && float16_is_zero(op1))) {
+        return float16_two;
+    }
+    return float16_sub(float16_two, float16_mul(op1, op2, stat), stat);
+}
+
+static float32 float32_recps_nf(float32 op1, float32 op2, float_status *stat)
+{
+    op1 = float32_squash_input_denormal(op1, stat);
+    op2 = float32_squash_input_denormal(op2, stat);
+
+    if ((float32_is_infinity(op1) && float32_is_zero(op2)) ||
+        (float32_is_infinity(op2) && float32_is_zero(op1))) {
+        return float32_two;
+    }
+    return float32_sub(float32_two, float32_mul(op1, op2, stat), stat);
+}
+
 #define DO_3OP(NAME, FUNC, TYPE) \
 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
 {                                                                          \
@@ -855,6 +883,9 @@ DO_3OP(gvec_fmaxnum_s, float32_maxnum, float32)
 DO_3OP(gvec_fminnum_h, float16_minnum, float16)
 DO_3OP(gvec_fminnum_s, float32_minnum, float32)
 
+DO_3OP(gvec_recps_nf_h, float16_recps_nf, float16)
+DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32)
+
 #ifdef TARGET_AARCH64
 
 DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
diff --git a/qemu/target/arm/vfp_helper.c b/qemu/target/arm/vfp_helper.c
index ed6dd0de..e4f7326b 100644
--- a/qemu/target/arm/vfp_helper.c
+++ b/qemu/target/arm/vfp_helper.c
@@ -538,19 +538,6 @@ uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float32 HELPER(recps_f32)(CPUARMState *env, float32 a, float32 b)
-{
-    float_status *s = &env->vfp.standard_fp_status;
-    if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
-        (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
-        if (!(float32_is_zero(a) || float32_is_zero(b))) {
-            float_raise(float_flag_input_denormal, s);
-        }
-        return float32_two;
-    }
-    return float32_sub(float32_two, float32_mul(a, b, s), s);
-}
-
 float32 HELPER(rsqrts_f32)(CPUARMState *env, float32 a, float32 b)
 {
     float_status *s = &env->vfp.standard_fp_status;
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 3b0fd832..45aeaf91 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -1379,6 +1379,8 @@
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_x86_64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_x86_64
 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_x86_64
+#define helper_gvec_recps_nf_h helper_gvec_recps_nf_h_x86_64
+#define helper_gvec_recps_nf_s helper_gvec_recps_nf_s_x86_64
 #define helper_gvec_rotl8i helper_gvec_rotl8i_x86_64
 #define helper_gvec_rotl16i helper_gvec_rotl16i_x86_64
 #define helper_gvec_rotl32i helper_gvec_rotl32i_x86_64