diff --git a/qemu/header_gen.py b/qemu/header_gen.py index c2eab7e6..b78927ee 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7094,6 +7094,18 @@ riscv_symbols = ( 'helper_vfsqrt_v_h', 'helper_vfsqrt_v_w', 'helper_vfsqrt_v_d', + 'helper_vfmin_vv_h', + 'helper_vfmin_vv_w', + 'helper_vfmin_vv_d', + 'helper_vfmax_vv_h', + 'helper_vfmax_vv_w', + 'helper_vfmax_vv_d', + 'helper_vfmin_vf_h', + 'helper_vfmin_vf_w', + 'helper_vfmin_vf_d', + 'helper_vfmax_vf_h', + 'helper_vfmax_vf_w', + 'helper_vfmax_vf_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 902367a2..2ed10014 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4530,6 +4530,18 @@ #define helper_vfsqrt_v_h helper_vfsqrt_v_h_riscv32 #define helper_vfsqrt_v_w helper_vfsqrt_v_w_riscv32 #define helper_vfsqrt_v_d helper_vfsqrt_v_d_riscv32 +#define helper_vfmin_vv_h helper_vfmin_vv_h_riscv32 +#define helper_vfmin_vv_w helper_vfmin_vv_w_riscv32 +#define helper_vfmin_vv_d helper_vfmin_vv_d_riscv32 +#define helper_vfmax_vv_h helper_vfmax_vv_h_riscv32 +#define helper_vfmax_vv_w helper_vfmax_vv_w_riscv32 +#define helper_vfmax_vv_d helper_vfmax_vv_d_riscv32 +#define helper_vfmin_vf_h helper_vfmin_vf_h_riscv32 +#define helper_vfmin_vf_w helper_vfmin_vf_w_riscv32 +#define helper_vfmin_vf_d helper_vfmin_vf_d_riscv32 +#define helper_vfmax_vf_h helper_vfmax_vf_h_riscv32 +#define helper_vfmax_vf_w helper_vfmax_vf_w_riscv32 +#define helper_vfmax_vf_d helper_vfmax_vf_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index ab297261..6727a1b5 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4530,6 +4530,18 @@ #define helper_vfsqrt_v_h helper_vfsqrt_v_h_riscv64 #define helper_vfsqrt_v_w helper_vfsqrt_v_w_riscv64 #define helper_vfsqrt_v_d helper_vfsqrt_v_d_riscv64 +#define helper_vfmin_vv_h helper_vfmin_vv_h_riscv64 +#define helper_vfmin_vv_w helper_vfmin_vv_w_riscv64 +#define helper_vfmin_vv_d helper_vfmin_vv_d_riscv64 +#define helper_vfmax_vv_h helper_vfmax_vv_h_riscv64 +#define helper_vfmax_vv_w helper_vfmax_vv_w_riscv64 +#define helper_vfmax_vv_d helper_vfmax_vv_d_riscv64 +#define helper_vfmin_vf_h helper_vfmin_vf_h_riscv64 +#define helper_vfmin_vf_w helper_vfmin_vf_w_riscv64 +#define helper_vfmin_vf_d helper_vfmin_vf_d_riscv64 +#define helper_vfmax_vf_h helper_vfmax_vf_h_riscv64 +#define helper_vfmax_vf_w helper_vfmax_vf_w_riscv64 +#define helper_vfmax_vf_d helper_vfmax_vf_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 420de83c..3a6af2c2 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -930,3 +930,16 @@ DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 0d58c4c5..854ff9a3 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -492,6 +492,10 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm +vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm +vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm +vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm +vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index bce868a9..71420cec 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2165,3 +2165,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check) + +/* Vector Floating-Point MIN/MAX Instructions */ +GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 674dd158..fe8bbc7f 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -3818,3 +3818,30 @@ RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) + +/* Vector Floating-Point MIN/MAX Instructions */ +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) +GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) +GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) + +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) +GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)