From f9c971653495205672d6cd4fb5eecf75c671036f Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 11:52:07 -0500 Subject: [PATCH] target/riscv: vector floating-point classify instructions Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c --- qemu/header_gen.py | 6 ++ qemu/riscv32.h | 6 ++ qemu/riscv64.h | 6 ++ qemu/target/riscv/fpu_helper.c | 33 +------ qemu/target/riscv/helper.h | 4 + qemu/target/riscv/insn32.decode | 1 + qemu/target/riscv/insn_trans/trans_rvv.inc.c | 3 + qemu/target/riscv/internals.h | 6 ++ qemu/target/riscv/vector_helper.c | 91 ++++++++++++++++++++ 9 files changed, 126 insertions(+), 30 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 20b82513..63827610 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6212,6 +6212,9 @@ riscv_symbols = ( 'decode_insn16', 'decode_insn32', 'do_raise_exception_err', + 'fclass_d_risc', + 'fclass_h_risc', + 'fclass_s_risc', 'gen_helper_tlb_flush', 'helper_csrrc', 'helper_csrrs', @@ -7160,6 +7163,9 @@ riscv_symbols = ( 'helper_vmford_vf_h', 'helper_vmford_vf_w', 'helper_vmford_vf_d', + 'helper_vfclass_v_h', + 'helper_vfclass_v_w', + 'helper_vfclass_v_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 91fb1bf3..2d7572e8 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -3648,6 +3648,9 @@ #define decode_insn16 decode_insn16_riscv32 #define decode_insn32 decode_insn32_riscv32 #define do_raise_exception_err do_raise_exception_err_riscv32 +#define fclass_d_risc fclass_d_risc_riscv32 +#define fclass_h_risc fclass_h_risc_riscv32 +#define fclass_s_risc fclass_s_risc_riscv32 #define gen_helper_tlb_flush gen_helper_tlb_flush_riscv32 #define helper_csrrc helper_csrrc_riscv32 #define helper_csrrs helper_csrrs_riscv32 @@ -4596,6 +4599,9 @@ #define helper_vmford_vf_h helper_vmford_vf_h_riscv32 #define helper_vmford_vf_w helper_vmford_vf_w_riscv32 #define helper_vmford_vf_d helper_vmford_vf_d_riscv32 +#define helper_vfclass_v_h helper_vfclass_v_h_riscv32 +#define helper_vfclass_v_w helper_vfclass_v_w_riscv32 +#define helper_vfclass_v_d helper_vfclass_v_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 20cd5716..ab38bcf7 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -3648,6 +3648,9 @@ #define decode_insn16 decode_insn16_riscv64 #define decode_insn32 decode_insn32_riscv64 #define do_raise_exception_err do_raise_exception_err_riscv64 +#define fclass_d_risc fclass_d_risc_riscv64 +#define fclass_h_risc fclass_h_risc_riscv64 +#define fclass_s_risc fclass_s_risc_riscv64 #define gen_helper_tlb_flush gen_helper_tlb_flush_riscv64 #define helper_csrrc helper_csrrc_riscv64 #define helper_csrrs helper_csrrs_riscv64 @@ -4596,6 +4599,9 @@ #define helper_vmford_vf_h helper_vmford_vf_h_riscv64 #define helper_vmford_vf_w helper_vmford_vf_w_riscv64 #define helper_vmford_vf_d helper_vmford_vf_d_riscv64 +#define helper_vfclass_v_h helper_vfclass_v_h_riscv64 +#define helper_vfclass_v_w helper_vfclass_v_w_riscv64 +#define helper_vfclass_v_d helper_vfclass_v_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/fpu_helper.c b/qemu/target/riscv/fpu_helper.c index 0b79562a..959d4c5b 100644 --- a/qemu/target/riscv/fpu_helper.c +++ b/qemu/target/riscv/fpu_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "internals.h" target_ulong riscv_cpu_get_fflags(CPURISCVState *env) { @@ -230,21 +231,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) target_ulong helper_fclass_s(uint64_t frs1) { - float32 f = frs1; - bool sign = float32_is_neg(f); - - if (float32_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float32_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float32_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } + return fclass_s_risc(frs1); } uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) @@ -353,19 +340,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) target_ulong helper_fclass_d(uint64_t frs1) { - float64 f = frs1; - bool sign = float64_is_neg(f); - - if (float64_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float64_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float64_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } + return fclass_d_risc(frs1); } diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 21d72fd6..b40b586a 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -999,3 +999,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 59fb1a24..6912eda2 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -514,6 +514,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm +vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index dd904f42..9152d92a 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2214,3 +2214,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) + +/* Vector Floating-Point Classify Instruction */ +GEN_OPFV_TRANS(vfclass_v, opfv_check) diff --git a/qemu/target/riscv/internals.h b/qemu/target/riscv/internals.h index e61d7b9c..8ea92089 100644 --- a/qemu/target/riscv/internals.h +++ b/qemu/target/riscv/internals.h @@ -28,4 +28,10 @@ FIELD(VDATA, LMUL, 9, 2) FIELD(VDATA, NF, 11, 4) FIELD(VDATA, WD, 11, 1) +/* float point classify helpers */ +// Unicorn: Given _risc prefixes to avoid header gen clashing +target_ulong fclass_h_risc(uint64_t frs1); +target_ulong fclass_s_risc(uint64_t frs1); +target_ulong fclass_d_risc(uint64_t frs1); + #endif diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 9cc1676e..08a81263 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4079,3 +4079,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) + +/* Vector Floating-Point Classify Instruction */ +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +target_ulong fclass_h_risc(uint64_t frs1) +{ + float16 f = frs1; + bool sign = float16_is_neg(f); + + if (float16_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float16_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float16_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float16_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +target_ulong fclass_s_risc(uint64_t frs1) +{ + float32 f = frs1; + bool sign = float32_is_neg(f); + + if (float32_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float32_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float32_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float32_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +target_ulong fclass_d_risc(uint64_t frs1) +{ + float64 f = frs1; + bool sign = float64_is_neg(f); + + if (float64_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float64_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float64_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float64_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h_risc) +RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s_risc) +RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d_risc) +GEN_VEXT_V(vfclass_v_h, 2, 2, clearh) +GEN_VEXT_V(vfclass_v_w, 4, 4, clearl) +GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)