diff --git a/qemu/hw/i386/pc.c b/qemu/hw/i386/pc.c
index 6377bee3..36c5f8cb 100644
--- a/qemu/hw/i386/pc.c
+++ b/qemu/hw/i386/pc.c
@@ -25,7 +25,9 @@
 
 #include "hw/hw.h"
 #include "hw/i386/pc.h"
+#include "sysemu/cpus.h"
 #include "sysemu/sysemu.h"
+#include "target-i386/topology.h"
 #include "qapi-visit.h"
 
 
@@ -179,3 +181,34 @@ void pc_machine_register_types(struct uc_struct *uc)
 {
     type_register_static(uc, &pc_machine_info);
 }
+
+/* Enables contiguous-apic-ID mode, for compatibility */
+static bool compat_apic_id_mode;
+
+void enable_compat_apic_id_mode(void)
+{
+    compat_apic_id_mode = true;
+}
+
+/* Calculates initial APIC ID for a specific CPU index
+ *
+ * Currently we need to be able to calculate the APIC ID from the CPU index
+ * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
+ * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
+ * all CPUs up to max_cpus.
+ */
+uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
+{
+    uint32_t correct_id;
+
+    correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
+    if (compat_apic_id_mode) {
+        if (cpu_index != correct_id) {
+            //error_report("APIC IDs set in compatibility mode, "
+            //        "CPU topology won't match the configuration");
+        }
+        return cpu_index;
+    } else {
+        return correct_id;
+    }
+}
diff --git a/qemu/target-i386/cpu.c b/qemu/target-i386/cpu.c
index ebf19ed7..d368d230 100644
--- a/qemu/target-i386/cpu.c
+++ b/qemu/target-i386/cpu.c
@@ -23,7 +23,6 @@
 
 #include "cpu.h"
 #include "sysemu/cpus.h"
-#include "topology.h"
 
 #include "qapi/qmp/qerror.h"
 
@@ -2432,37 +2431,6 @@ out:
     return 0;
 }
 
-/* Enables contiguous-apic-ID mode, for compatibility */
-static bool compat_apic_id_mode;
-
-void enable_compat_apic_id_mode(void)
-{
-    compat_apic_id_mode = true;
-}
-
-/* Calculates initial APIC ID for a specific CPU index
- *
- * Currently we need to be able to calculate the APIC ID from the CPU index
- * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
- * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
- * all CPUs up to max_cpus.
- */
-uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
-{
-    uint32_t correct_id;
-
-    correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
-    if (compat_apic_id_mode) {
-        if (cpu_index != correct_id) {
-            //error_report("APIC IDs set in compatibility mode, "
-            //        "CPU topology won't match the configuration");
-        }
-        return cpu_index;
-    } else {
-        return correct_id;
-    }
-}
-
 static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
 {
     //printf("... X86 initialize (object)\n");