From fce8138187dacccad1a725672d62bfeb724bdd47 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 2 Mar 2018 13:47:08 -0500 Subject: [PATCH] armv7m: Report no-coprocessor faults correctly For v7M attempts to access a nonexistent coprocessor are reported differently from plain undefined instructions (as UsageFaults of type NOCP rather than type UNDEFINSTR). Split them out into a new EXCP_NOCP so we can report the FSR value correctly. Backports commit 7517748e3f71a3099e57915fba95c4c308e6d842 from qemu --- qemu/target/arm/cpu.h | 1 + qemu/target/arm/helper.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 5a3acf53..3a47d51c 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -60,6 +60,7 @@ #define EXCP_VIRQ 14 #define EXCP_VFIQ 15 #define EXCP_SEMIHOST 16 /* semihosting call */ +#define EXCP_NOCP 17 /* v7M NOCP UsageFault */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 74fd5db4..18b108b9 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -5445,6 +5445,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; return; + case EXCP_NOCP: + //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); + env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; + return; case EXCP_SWI: /* The PC already points to the next instruction. */ //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);