diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index 0b7eab1b..5c2f82db 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -1949,7 +1949,8 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
         cpu->isar.id_isar6 = t;
 
         t = cpu->isar.mvfr1;
-        t = FIELD_DP32(t, MVFR1, FPHP, 2);     /* v8.0 FP support */
+        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
         cpu->isar.mvfr1 = t;
 
         t = cpu->isar.mvfr2;
diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c
index 6301a718..0014c64e 100644
--- a/qemu/target/arm/cpu64.c
+++ b/qemu/target/arm/cpu64.c
@@ -356,13 +356,11 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
     cpu->isar.id_dfr0 = u;
 
-    // Unicorn: we lie and enable them anyway
-    /*
-     * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
-     * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
-     * but it is also not legal to enable SVE without support for FP16,
-     * and enabling SVE in system mode is more useful in the short term.
-     */
+    u = cpu->isar.mvfr1;
+    u = FIELD_DP32(u, MVFR1, FPHP, 3);      /* v8.2-FP16 */
+    u = FIELD_DP32(u, MVFR1, SIMDHP, 2);    /* v8.2-FP16 */
+    cpu->isar.mvfr1 = u;
+
     /* For usermode -cpu max we can use a larger and more efficient DCZ
      * blocksize since we don't have to follow what the hardware does.
      */