# Thumb1 instructions # # Copyright (c) 2019 Linaro, Ltd # # This library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public # License as published by the Free Software Foundation; either # version 2 of the License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # # This file is processed by scripts/decodetree.py # &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list # Set S if the instruction is outside of an IT block. %s !function=t16_setflags # Data-processing (two low registers) %reg_0 0:3 @lll_noshr ...... .... rm:3 rd:3 \ &s_rrr_shi %s rn=%reg_0 shim=0 shty=0 @xll_noshr ...... .... rm:3 rn:3 \ &s_rrr_shi s=1 rd=0 shim=0 shty=0 @lxl_shr ...... .... rs:3 rd:3 \ &s_rrr_shr %s rm=%reg_0 rn=0 AND_rrri 010000 0000 ... ... @lll_noshr EOR_rrri 010000 0001 ... ... @lll_noshr MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR ADC_rrri 010000 0101 ... ... @lll_noshr SBC_rrri 010000 0110 ... ... @lll_noshr MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR TST_xrri 010000 1000 ... ... @xll_noshr RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 CMP_xrri 010000 1010 ... ... @xll_noshr CMN_xrri 010000 1011 ... ... @xll_noshr ORR_rrri 010000 1100 ... ... @lll_noshr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr # Load/store (register offset) @ldst_rr ....... rm:3 rn:3 rt:3 \ &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0 STR_rr 0101 000 ... ... ... @ldst_rr STRH_rr 0101 001 ... ... ... @ldst_rr STRB_rr 0101 010 ... ... ... @ldst_rr LDRSB_rr 0101 011 ... ... ... @ldst_rr LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr # Load/store word/byte (immediate offset) %imm5_6x4 6:5 !function=times_4 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \ &ldst_ri p=1 w=0 u=1 @ldst_ri_4 ..... ..... rn:3 rt:3 \ &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 STR_ri 01100 ..... ... ... @ldst_ri_4 LDR_ri 01101 ..... ... ... @ldst_ri_4 STRB_ri 01110 ..... ... ... @ldst_ri_1 LDRB_ri 01111 ..... ... ... @ldst_ri_1 # Load/store halfword (immediate offset) %imm5_6x2 6:5 !function=times_2 @ldst_ri_2 ..... ..... rn:3 rt:3 \ &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 STRH_ri 10000 ..... ... ... @ldst_ri_2 LDRH_ri 10001 ..... ... ... @ldst_ri_2 # Load/store (SP-relative) %imm8_0x4 0:8 !function=times_4 @ldst_spec_i ..... rt:3 ........ \ &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 # Add PC/SP (immediate) ADR 10100 rd:3 ........ imm=%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP # Load/store multiple @ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1 STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \ &s_rrr_shi %s shim=0 shty=0 ADD_rrri 0001100 ... ... ... @addsub_3 SUB_rrri 0001101 ... ... ... @addsub_3 # Add/subtract (two low registers and immediate) @addsub_2i ....... imm:3 rn:3 rd:3 \ &s_rri_rot %s rot=0 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i