From 84eb3e7d02d386bc90eb4a6c6b6e33eea33a42e2 Mon Sep 17 00:00:00 2001
From: jam1garner <8260240+jam1garner@users.noreply.github.com>
Date: Sun, 21 Nov 2021 21:10:14 -0500
Subject: [PATCH 1/3] arm: dynarmic: Implement icache op handling for 'ic ivau'
instruction
---
src/core/arm/dynarmic/arm_dynarmic_64.cpp | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 4e73cc03a..587fffb34 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -86,6 +86,24 @@ public:
num_instructions, MemoryReadCode(pc));
}
+ void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
+ VAddr value) override {
+ constexpr u64 ICACHE_LINE_SIZE = 64;
+ u64 cache_line_start;
+
+ switch (op) {
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
+ cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
+ parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ return;
+
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
+ default:
+ LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
+ }
+ }
+
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
switch (exception) {
case Dynarmic::A64::Exception::WaitForInterrupt:
From c8a67a725de6481c891d5bfe1b83fcb6340c88a3 Mon Sep 17 00:00:00 2001
From: jam1garner <8260240+jam1garner@users.noreply.github.com>
Date: Sun, 21 Nov 2021 21:18:56 -0500
Subject: [PATCH 2/3] arm: dynarmic: Implement icache op handling for 'ic
iallu' instruction
---
src/core/arm/dynarmic/arm_dynarmic_64.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 587fffb34..8fe83413c 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -98,6 +98,9 @@ public:
return;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
+ parent.ClearInstructionCache();
+ return;
+
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
From 4d9c9e567ef6c44967b639471613a0328dcbf833 Mon Sep 17 00:00:00 2001
From: jam1garner <8260240+jam1garner@users.noreply.github.com>
Date: Sun, 21 Nov 2021 21:24:07 -0500
Subject: [PATCH 3/3] arm: dynarmic: Cleanup icache op handling
---
src/core/arm/dynarmic/arm_dynarmic_64.cpp | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 8fe83413c..56836bd05 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -88,22 +88,21 @@ public:
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
VAddr value) override {
- constexpr u64 ICACHE_LINE_SIZE = 64;
- u64 cache_line_start;
-
switch (op) {
- case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
- cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
- parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
- return;
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
+ static constexpr u64 ICACHE_LINE_SIZE = 64;
+ const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
+ parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ break;
+ }
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache();
- return;
-
+ break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
- LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
+ LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
+ break;
}
}