shld and lhld

This commit is contained in:
Martin Löffler 2023-01-26 06:57:46 +01:00
parent 2fff8d2448
commit eb993eb1b4
Signed by: FatalErrorCoded
GPG key ID: FFEF368AC076566A
2 changed files with 21 additions and 1 deletions

View file

@ -1,4 +1,4 @@
use crate::{get_register, set_register, structs::get_register_pair, EmulatorState, Register}; use crate::{get_register, get_register_pair, set_register, EmulatorState, Register};
/// Move (copy) value from source to destination register /// Move (copy) value from source to destination register
pub fn mov(src: Register, dest: Register, state: &mut EmulatorState) { pub fn mov(src: Register, dest: Register, state: &mut EmulatorState) {
@ -22,3 +22,15 @@ pub fn ldax(register: Register, state: &mut EmulatorState) {
let address = get_register_pair(register, state); let address = get_register_pair(register, state);
state.a = state.memory[address as usize]; state.a = state.memory[address as usize];
} }
/// Store a 16-bit word from H and L to the specified address
pub fn shld(address: u16, state: &mut EmulatorState) {
state.memory[address as usize] = state.l;
state.memory[address as usize + 1] = state.h;
}
/// Load a 16-bit word into H and L from the specified address
pub fn lhld(address: u16, state: &mut EmulatorState) {
state.l = state.memory[address as usize];
state.h = state.memory[address as usize + 1];
}

View file

@ -90,6 +90,14 @@ fn tick(state: &mut EmulatorState) {
0x32 => state.memory[state.next_word() as usize] = state.a, // STA 0x32 => state.memory[state.next_word() as usize] = state.a, // STA
0x3a => state.a = state.memory[state.next_word() as usize], // LDA 0x3a => state.a = state.memory[state.next_word() as usize], // LDA
// 16-bit transfer instructions
0x01 => set_register_pair(Register::B, state.next_word(), state), // LXI B
0x11 => set_register_pair(Register::D, state.next_word(), state), // LXI D
0x21 => set_register_pair(Register::H, state.next_word(), state), // LXI H
0x31 => set_register_pair(Register::SP, state.next_word(), state), // LXI SP
0x22 => transfer::shld(state.next_word(), state), // SHLD
0x2a => transfer::lhld(state.next_word(), state), // LHLD
/* Maths */ /* Maths */
// INR // INR
0x04 => arithmetic::inr(Register::B, state), 0x04 => arithmetic::inr(Register::B, state),