INR and DCR

This commit is contained in:
Lea 2023-01-25 20:18:31 +01:00
parent d7871531ea
commit 27c6c10c1f
Signed by: Lea
GPG key ID: 1BAFFE8347019C42
3 changed files with 40 additions and 6 deletions

View file

@ -1,4 +1,4 @@
use crate::{EmulatorState, Register, get_register};
use crate::{EmulatorState, Register, get_register, structs::set_register};
/// Sets the condition code flags according to `result`. `flags` parameter
/// indicates which flags will be set, 0b1111 will set all (Z, S, C, P)
@ -12,7 +12,7 @@ fn set_cc(state: &mut EmulatorState, result: u16, flags: u8) {
/// Add values of `register` and `A`
pub fn add(register: Register, state: &mut EmulatorState) {
let result = get_register(register, state) as u16 + state.a as u16;
let result = get_register(&register, state) as u16 + state.a as u16;
set_cc(state, result, 0b1111);
state.a = (result & 0xff) as u8;
}
@ -26,7 +26,7 @@ pub fn adi(byte: u8, state: &mut EmulatorState) {
/// Add values of `register` and `A` and add +1 if carry bit is set
pub fn adc(register: Register, state: &mut EmulatorState) {
let result = get_register(register, state) as u16 + state.a as u16 + if state.cc.c { 1 } else { 0 };
let result = get_register(&register, state) as u16 + state.a as u16 + if state.cc.c { 1 } else { 0 };
set_cc(state, result, 0b1111);
state.a = (result & 0xff) as u8;
}
@ -53,3 +53,17 @@ pub fn dad(register: Register, state: &mut EmulatorState) {
state.h = (result >> 8) as u8;
state.l = result as u8;
}
/// Increase register
pub fn inr(register: Register, state: &mut EmulatorState) {
let (result, _) = get_register(&register, state).overflowing_add(1);
set_cc(state, result as u16, 0b1101);
set_register(&register, result, state);
}
/// Decrease register
pub fn dcr(register: Register, state: &mut EmulatorState) {
let (result, _) = get_register(&register, state).overflowing_sub(1);
set_cc(state, result as u16, 0b1101);
set_register(&register, result, state);
}

View file

@ -54,7 +54,27 @@ fn tick(state: &mut EmulatorState) {
match instruction {
0x00 => {} // NOP
/* ADD */
/* Maths */
// INR
0x04 => arithmetic::inr(Register::B, state),
0x0c => arithmetic::inr(Register::C, state),
0x14 => arithmetic::inr(Register::D, state),
0x1c => arithmetic::inr(Register::E, state),
0x24 => arithmetic::inr(Register::H, state),
0x2c => arithmetic::inr(Register::L, state),
0x34 => arithmetic::inr(Register::M, state),
0x3c => arithmetic::inr(Register::A, state),
// DCR
0x05 => arithmetic::dcr(Register::B, state),
0x0d => arithmetic::dcr(Register::C, state),
0x15 => arithmetic::dcr(Register::D, state),
0x1d => arithmetic::dcr(Register::E, state),
0x25 => arithmetic::dcr(Register::H, state),
0x2d => arithmetic::dcr(Register::L, state),
0x35 => arithmetic::dcr(Register::M, state),
0x3d => arithmetic::dcr(Register::A, state),
// DAD
0x09 => arithmetic::dad(Register::B, state),

View file

@ -58,7 +58,7 @@ pub fn register_from_num(b: u8) -> Register {
}
}
pub fn get_register(register: Register, state: &EmulatorState) -> u8 {
pub fn get_register(register: &Register, state: &EmulatorState) -> u8 {
match register {
Register::B => state.b as u8,
Register::C => state.c as u8,
@ -72,7 +72,7 @@ pub fn get_register(register: Register, state: &EmulatorState) -> u8 {
}
}
pub fn set_register(register: Register, value: u8, state: &mut EmulatorState) {
pub fn set_register(register: &Register, value: u8, state: &mut EmulatorState) {
match register {
Register::B => state.b = value,
Register::C => state.c = value,