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Merge pull request #349 from lioncash/uhdync
dyncom: Implement UHADD8, UHADD16, UHSUB8, UHSUB16, UHASX, and UHSAX
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commit
28e64806cd
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@ -3086,15 +3086,47 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index)
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inst_base->load_r15 = 1;
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UADDSUBX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHADDSUBX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHSUB16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("UHSUBADDX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->op1 = BITS(inst, 20, 21);
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inst_cream->op2 = BITS(inst, 5, 7);
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umaal_inst));
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@ -6622,15 +6654,95 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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UADD16_INST:
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UADD8_INST:
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UADD16_INST:
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UADDSUBX_INST:
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UHADD16_INST:
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UHADD8_INST:
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UHADD16_INST:
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UHADDSUBX_INST:
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UHSUB16_INST:
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UHSUB8_INST:
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UHSUBADDX_INST:
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UHSUB8_INST:
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UHSUB16_INST:
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{
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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const u8 op2 = inst_cream->op2;
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if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03)
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{
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u32 lo_val = 0;
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u32 hi_val = 0;
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// UHADD16
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if (op2 == 0x00) {
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lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
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}
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// UHASX
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else if (op2 == 0x01) {
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lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
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}
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// UHSAX
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else if (op2 == 0x02) {
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lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
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}
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// UHSUB16
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else if (op2 == 0x03) {
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lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
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}
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lo_val >>= 1;
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hi_val >>= 1;
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RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16);
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}
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else if (op2 == 0x04 || op2 == 0x07) {
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u32 sum1;
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u32 sum2;
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u32 sum3;
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u32 sum4;
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// UHADD8
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if (op2 == 0x04) {
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sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
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sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
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sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
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sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
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}
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// UHSUB8
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else {
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sum1 = (rn_val & 0xFF) - (rm_val & 0xFF);
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sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
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sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
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sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
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}
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sum1 >>= 1;
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sum2 >>= 1;
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sum3 >>= 1;
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sum4 >>= 1;
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RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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UMAAL_INST:
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{
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INC_ICOUNTER;
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