mirror of
https://github.com/citra-emu/citra-nightly.git
synced 2024-12-25 04:25:34 +00:00
Merge pull request #685 from lioncash/cpregs
dyncom: Set the MPCore CP15 register reset values on initialization.
This commit is contained in:
bunnei
commit
14dcd98653
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@ -6,6 +6,7 @@
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#include "common/common.h"
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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namespace Core {
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struct ThreadContext;
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@ -73,6 +74,20 @@ public:
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*/
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virtual void SetCPSR(u32 cpsr) = 0;
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/**
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* Gets the value stored in a CP15 register.
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* @param reg The CP15 register to retrieve the value from.
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* @return the value stored in the given CP15 register.
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*/
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virtual u32 GetCP15Register(CP15Register reg) = 0;
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/**
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* Stores the given value into the indicated CP15 register.
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* @param reg The CP15 register to store the value into.
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* @param value The value to store into the CP15 register.
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*/
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virtual void SetCP15Register(CP15Register reg, u32 value) = 0;
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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@ -68,6 +68,14 @@ void ARM_DynCom::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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u32 ARM_DynCom::GetCP15Register(CP15Register reg) {
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return state->CP15[reg];
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}
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void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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state->CP15[reg] = value;
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}
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void ARM_DynCom::AddTicks(u64 ticks) {
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down_count -= ticks;
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if (down_count < 0)
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@ -22,6 +22,8 @@ public:
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void SetReg(int index, u32 value) override;
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u32 GetCPSR() const override;
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void SetCPSR(u32 cpsr) override;
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u32 GetCP15Register(CP15Register reg) override;
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void SetCP15Register(CP15Register reg, u32 value) override;
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void AddTicks(u64 ticks) override;
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@ -3700,7 +3700,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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#define OPCODE_1 inst_cream->opcode_1
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#define OPCODE_2 inst_cream->opcode_2
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#define CRm inst_cream->crm
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#define CP15_REG(n) cpu->CP15[CP15(n)]
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#define RD cpu->Reg[inst_cream->Rd]
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#define RD2 cpu->Reg[inst_cream->Rd + 1]
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#define RN cpu->Reg[inst_cream->Rn]
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@ -16,6 +16,7 @@
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <cstring>
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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@ -66,6 +67,64 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
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ARMul_CoProInit(state);
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}
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// Resets certain MPCore CP15 values to their ARM-defined reset values.
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static void ResetMPCoreCP15Registers(ARMul_State* cpu)
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{
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// c0
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cpu->CP15[CP15_MAIN_ID] = 0x410FB024;
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cpu->CP15[CP15_TLB_TYPE] = 0x00000800;
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cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111;
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cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001;
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cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000;
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cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000;
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cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011;
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cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111;
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cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011;
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cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131;
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cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141;
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// c1
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cpu->CP15[CP15_CONTROL] = 0x00054078;
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cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F;
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cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000;
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// c2
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000;
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000;
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cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000;
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// c3
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cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000;
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// c7
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cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000;
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// c9
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cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0;
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// c10
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cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000;
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cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4;
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cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0;
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// c13
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cpu->CP15[CP15_PID] = 0x00000000;
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cpu->CP15[CP15_CONTEXT_ID] = 0x00000000;
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cpu->CP15[CP15_THREAD_UPRW] = 0x00000000;
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cpu->CP15[CP15_THREAD_URO] = 0x00000000;
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cpu->CP15[CP15_THREAD_PRW] = 0x00000000;
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// c15
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cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000;
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cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000;
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cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000;
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}
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/***************************************************************************\
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* Call this routine to set up the initial machine state (or perform a RESET *
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\***************************************************************************/
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@ -80,6 +139,8 @@ void ARMul_Reset(ARMul_State* state)
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state->Bank = SVCBANK;
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FLUSHPIPE;
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ResetMPCoreCP15Registers(state);
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state->EndCondition = 0;
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state->ErrorCode = 0;
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@ -225,13 +225,10 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod
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if (crn == 13 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_THREAD_UPRW)];
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return cpu->CP15[CP15_THREAD_UPRW];
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// TODO: Whenever TLS is implemented, this should return
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// "cpu->CP15[CP15(CP15_THREAD_URO)];"
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// which contains the address of the 0x200-byte TLS
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if (opcode_2 == 3)
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return Memory::KERNEL_MEMORY_VADDR;
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return cpu->CP15[CP15_THREAD_URO];
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}
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if (InAPrivilegedMode(cpu))
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@ -241,135 +238,135 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod
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if (crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_MAIN_ID)];
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return cpu->CP15[CP15_MAIN_ID];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CACHE_TYPE)];
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return cpu->CP15[CP15_CACHE_TYPE];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_TLB_TYPE)];
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return cpu->CP15[CP15_TLB_TYPE];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_CPU_ID)];
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return cpu->CP15[CP15_CPU_ID];
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}
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else if (crm == 1)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)];
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return cpu->CP15[CP15_PROCESSOR_FEATURE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)];
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return cpu->CP15[CP15_PROCESSOR_FEATURE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)];
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return cpu->CP15[CP15_DEBUG_FEATURE_0];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)];
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)];
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1];
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if (opcode_2 == 6)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)];
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2];
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if (opcode_2 == 7)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)];
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return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3];
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}
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else if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_0)];
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return cpu->CP15[CP15_ISA_FEATURE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_1)];
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return cpu->CP15[CP15_ISA_FEATURE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_2)];
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return cpu->CP15[CP15_ISA_FEATURE_2];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_3)];
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return cpu->CP15[CP15_ISA_FEATURE_3];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_4)];
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return cpu->CP15[CP15_ISA_FEATURE_4];
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}
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}
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_CONTROL)];
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return cpu->CP15[CP15_CONTROL];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
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return cpu->CP15[CP15_AUXILIARY_CONTROL];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
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return cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL];
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}
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if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
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return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
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return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
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return cpu->CP15[CP15_TRANSLATION_BASE_CONTROL];
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}
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if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
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return cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL];
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if (crn == 5 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_STATUS)];
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return cpu->CP15[CP15_FAULT_STATUS];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
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return cpu->CP15[CP15_INSTR_FAULT_STATUS];
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}
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if (crn == 6 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
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return cpu->CP15[CP15_FAULT_ADDRESS];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_WFAR)];
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return cpu->CP15[CP15_WFAR];
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}
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if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PHYS_ADDRESS)];
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return cpu->CP15[CP15_PHYS_ADDRESS];
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if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)];
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return cpu->CP15[CP15_DATA_CACHE_LOCKDOWN];
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if (crn == 10 && opcode_1 == 0)
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{
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if (crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)];
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return cpu->CP15[CP15_TLB_LOCKDOWN];
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if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)];
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return cpu->CP15[CP15_PRIMARY_REGION_REMAP];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)];
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return cpu->CP15[CP15_NORMAL_REGION_REMAP];
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}
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}
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if (crn == 13 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PID)];
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return cpu->CP15[CP15_PID];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CONTEXT_ID)];
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return cpu->CP15[CP15_CONTEXT_ID];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_THREAD_PRW)];
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return cpu->CP15[CP15_THREAD_PRW];
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}
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if (crn == 15)
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@ -377,32 +374,32 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod
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if (opcode_1 == 0 && crm == 12)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)];
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return cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CYCLE_COUNTER)];
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return cpu->CP15[CP15_CYCLE_COUNTER];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COUNT_0)];
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return cpu->CP15[CP15_COUNT_0];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_COUNT_1)];
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return cpu->CP15[CP15_COUNT_1];
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}
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if (opcode_1 == 5 && opcode_2 == 2)
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{
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if (crm == 5)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)];
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS];
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if (crm == 6)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)];
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS];
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if (crm == 7)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)];
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return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE];
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}
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if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)];
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return cpu->CP15[CP15_TLB_DEBUG_CONTROL];
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}
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}
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@ -420,38 +417,38 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15(CP15_CONTROL)] = value;
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cpu->CP15[CP15_CONTROL] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = value;
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cpu->CP15[CP15_AUXILIARY_CONTROL] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = value;
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cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value;
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}
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else if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = value;
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = value;
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else if (opcode_2 == 1)
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cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = value;
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cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = value;
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else if (opcode_2 == 2)
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cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = value;
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cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = value;
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}
|
||||
else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = value;
|
||||
cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = value;
|
||||
}
|
||||
else if (crn == 5 && opcode_1 == 0 && crm == 0)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_FAULT_STATUS)] = value;
|
||||
cpu->CP15[CP15_FAULT_STATUS] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = value;
|
||||
cpu->CP15[CP15_INSTR_FAULT_STATUS] = value;
|
||||
}
|
||||
else if (crn == 6 && opcode_1 == 0 && crm == 0)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = value;
|
||||
cpu->CP15[CP15_FAULT_ADDRESS] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_WFAR)] = value;
|
||||
cpu->CP15[CP15_WFAR] = value;
|
||||
}
|
||||
else if (crn == 7 && opcode_1 == 0)
|
||||
{
|
||||
|
|
@ -459,56 +456,56 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
|
|||
|
||||
if (crm == 0 && opcode_2 == 4)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_WAIT_FOR_INTERRUPT)] = value;
|
||||
cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value;
|
||||
}
|
||||
else if (crm == 4 && opcode_2 == 0)
|
||||
{
|
||||
// NOTE: Not entirely accurate. This should do permission checks.
|
||||
cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = Memory::VirtualToPhysicalAddress(value);
|
||||
cpu->CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value);
|
||||
}
|
||||
else if (crm == 5)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_INSTR_CACHE] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_MVA)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_INDEX)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value;
|
||||
else if (opcode_2 == 6)
|
||||
cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE)] = value;
|
||||
cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value;
|
||||
else if (opcode_2 == 7)
|
||||
cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY)] = value;
|
||||
cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value;
|
||||
}
|
||||
else if (crm == 6)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DATA_CACHE] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
|
||||
}
|
||||
else if (crm == 7 && opcode_2 == 0)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DATA_AND_INSTR_CACHE)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value;
|
||||
}
|
||||
else if (crm == 10)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE)] = value;
|
||||
cpu->CP15[CP15_CLEAN_DATA_CACHE] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_MVA)] = value;
|
||||
cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX)] = value;
|
||||
cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value;
|
||||
}
|
||||
else if (crm == 14)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE)] = value;
|
||||
cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
|
||||
cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
|
||||
cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value;
|
||||
}
|
||||
}
|
||||
else if (crn == 8 && opcode_1 == 0)
|
||||
|
|
@ -518,104 +515,104 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
|
|||
if (crm == 5)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_ITLB)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_ITLB] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_ITLB_SINGLE_ENTRY)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value;
|
||||
else if (opcode_2 == 3)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_MVA)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value;
|
||||
}
|
||||
else if (crm == 6)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DTLB)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DTLB] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DTLB_SINGLE_ENTRY)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value;
|
||||
else if (opcode_2 == 3)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_MVA)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value;
|
||||
}
|
||||
else if (crm == 7)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_UTLB)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_UTLB] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_UTLB_SINGLE_ENTRY)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value;
|
||||
else if (opcode_2 == 3)
|
||||
cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_MVA)] = value;
|
||||
cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value;
|
||||
}
|
||||
}
|
||||
else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = value;
|
||||
cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = value;
|
||||
}
|
||||
else if (crn == 10 && opcode_1 == 0)
|
||||
{
|
||||
if (crm == 0 && opcode_2 == 0)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = value;
|
||||
cpu->CP15[CP15_TLB_LOCKDOWN] = value;
|
||||
}
|
||||
else if (crm == 2)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = value;
|
||||
cpu->CP15[CP15_PRIMARY_REGION_REMAP] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = value;
|
||||
cpu->CP15[CP15_NORMAL_REGION_REMAP] = value;
|
||||
}
|
||||
}
|
||||
else if (crn == 13 && opcode_1 == 0 && crm == 0)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_PID)] = value;
|
||||
cpu->CP15[CP15_PID] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_CONTEXT_ID)] = value;
|
||||
cpu->CP15[CP15_CONTEXT_ID] = value;
|
||||
else if (opcode_2 == 3)
|
||||
cpu->CP15[CP15(CP15_THREAD_URO)] = value;
|
||||
cpu->CP15[CP15_THREAD_URO] = value;
|
||||
else if (opcode_2 == 4)
|
||||
cpu->CP15[CP15(CP15_THREAD_PRW)] = value;
|
||||
cpu->CP15[CP15_THREAD_PRW] = value;
|
||||
}
|
||||
else if (crn == 15)
|
||||
{
|
||||
if (opcode_1 == 0 && crm == 12)
|
||||
{
|
||||
if (opcode_2 == 0)
|
||||
cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = value;
|
||||
cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value;
|
||||
else if (opcode_2 == 1)
|
||||
cpu->CP15[CP15(CP15_CYCLE_COUNTER)] = value;
|
||||
cpu->CP15[CP15_CYCLE_COUNTER] = value;
|
||||
else if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_COUNT_0)] = value;
|
||||
cpu->CP15[CP15_COUNT_0] = value;
|
||||
else if (opcode_2 == 3)
|
||||
cpu->CP15[CP15(CP15_COUNT_1)] = value;
|
||||
cpu->CP15[CP15_COUNT_1] = value;
|
||||
}
|
||||
else if (opcode_1 == 5)
|
||||
{
|
||||
if (crm == 4)
|
||||
{
|
||||
if (opcode_2 == 2)
|
||||
cpu->CP15[CP15(CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
|
||||
cpu->CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
||||
else if (opcode_2 == 4)
|
||||
cpu->CP15[CP15(CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
|
||||
cpu->CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value;
|
||||
}
|
||||
else if (crm == 5 && opcode_2 == 2)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = value;
|
||||
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value;
|
||||
}
|
||||
else if (crm == 6 && opcode_2 == 2)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = value;
|
||||
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value;
|
||||
}
|
||||
else if (crm == 7 && opcode_2 == 2)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = value;
|
||||
cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value;
|
||||
}
|
||||
}
|
||||
else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = value;
|
||||
cpu->CP15[CP15_TLB_DEBUG_CONTROL] = value;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -623,18 +620,18 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
|
|||
// Unprivileged registers
|
||||
if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value;
|
||||
cpu->CP15[CP15_FLUSH_PREFETCH_BUFFER] = value;
|
||||
}
|
||||
else if (crn == 7 && opcode_1 == 0 && crm == 10)
|
||||
{
|
||||
if (opcode_2 == 4)
|
||||
cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value;
|
||||
cpu->CP15[CP15_DATA_SYNC_BARRIER] = value;
|
||||
else if (opcode_2 == 5)
|
||||
cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value;
|
||||
cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value;
|
||||
|
||||
}
|
||||
else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
|
||||
{
|
||||
cpu->CP15[CP15(CP15_THREAD_UPRW)] = value;
|
||||
cpu->CP15[CP15_THREAD_UPRW] = value;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,17 +51,23 @@ enum {
|
|||
EXCLUSIVE_STATE,
|
||||
EXCLUSIVE_RESULT,
|
||||
|
||||
// VFP registers
|
||||
VFP_BASE,
|
||||
VFP_FPSID = VFP_BASE,
|
||||
VFP_FPSCR,
|
||||
VFP_FPEXC,
|
||||
|
||||
MAX_REG_NUM,
|
||||
};
|
||||
|
||||
enum CP15Register {
|
||||
// c0 - Information registers
|
||||
CP15_BASE,
|
||||
CP15_C0 = CP15_BASE,
|
||||
CP15_C0_C0 = CP15_C0,
|
||||
CP15_MAIN_ID = CP15_C0_C0,
|
||||
CP15_MAIN_ID,
|
||||
CP15_CACHE_TYPE,
|
||||
CP15_TCM_STATUS,
|
||||
CP15_TLB_TYPE,
|
||||
CP15_CPU_ID,
|
||||
CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
|
||||
CP15_PROCESSOR_FEATURE_0,
|
||||
CP15_PROCESSOR_FEATURE_1,
|
||||
CP15_DEBUG_FEATURE_0,
|
||||
CP15_AUXILIARY_FEATURE_0,
|
||||
|
|
@ -69,24 +75,19 @@ enum {
|
|||
CP15_MEMORY_MODEL_FEATURE_1,
|
||||
CP15_MEMORY_MODEL_FEATURE_2,
|
||||
CP15_MEMORY_MODEL_FEATURE_3,
|
||||
CP15_C0_C2,
|
||||
CP15_ISA_FEATURE_0 = CP15_C0_C2,
|
||||
CP15_ISA_FEATURE_0,
|
||||
CP15_ISA_FEATURE_1,
|
||||
CP15_ISA_FEATURE_2,
|
||||
CP15_ISA_FEATURE_3,
|
||||
CP15_ISA_FEATURE_4,
|
||||
|
||||
// c1 - Control registers
|
||||
CP15_C1_C0,
|
||||
CP15_CONTROL = CP15_C1_C0,
|
||||
CP15_CONTROL,
|
||||
CP15_AUXILIARY_CONTROL,
|
||||
CP15_COPROCESSOR_ACCESS_CONTROL,
|
||||
|
||||
// c2 - Translation table registers
|
||||
CP15_C2,
|
||||
CP15_C2_C0 = CP15_C2,
|
||||
CP15_TRANSLATION_BASE = CP15_C2_C0,
|
||||
CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
|
||||
CP15_TRANSLATION_BASE_TABLE_0,
|
||||
CP15_TRANSLATION_BASE_TABLE_1,
|
||||
CP15_TRANSLATION_BASE_CONTROL,
|
||||
CP15_DOMAIN_ACCESS_CONTROL,
|
||||
|
|
@ -171,14 +172,9 @@ enum {
|
|||
CP15_TLB_FAULT_ADDR,
|
||||
CP15_TLB_FAULT_STATUS,
|
||||
|
||||
// VFP registers
|
||||
VFP_BASE,
|
||||
VFP_FPSID = VFP_BASE,
|
||||
VFP_FPSCR,
|
||||
VFP_FPEXC,
|
||||
|
||||
MAX_REG_NUM,
|
||||
// Not an actual register.
|
||||
// All registers should be defined above this.
|
||||
CP15_REGISTER_COUNT,
|
||||
};
|
||||
|
||||
#define CP15(idx) (idx - CP15_BASE)
|
||||
#define VFP_OFFSET(x) (x - VFP_BASE)
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ struct ARMul_State
|
|||
ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode
|
||||
ARMword exclusive_state;
|
||||
ARMword exclusive_result;
|
||||
ARMword CP15[VFP_BASE - CP15_BASE];
|
||||
ARMword CP15[CP15_REGISTER_COUNT];
|
||||
ARMword VFP[3]; // FPSID, FPSCR, and FPEXC
|
||||
// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
|
||||
// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include "core/core.h"
|
||||
#include "core/core_timing.h"
|
||||
|
||||
#include "core/mem_map.h"
|
||||
#include "core/settings.h"
|
||||
#include "core/arm/arm_interface.h"
|
||||
#include "core/arm/disassembler/arm_disasm.h"
|
||||
|
|
@ -59,6 +60,10 @@ int Init() {
|
|||
g_sys_core = new ARM_DynCom(USER32MODE);
|
||||
g_app_core = new ARM_DynCom(USER32MODE);
|
||||
|
||||
// TODO: Whenever TLS is implemented, this should contain
|
||||
// the address of the 0x200-byte TLS
|
||||
g_app_core->SetCP15Register(CP15_THREAD_URO, Memory::KERNEL_MEMORY_VADDR);
|
||||
|
||||
LOG_DEBUG(Core, "Initialized OK");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue