mirror of
https://github.com/citra-emu/citra-nightly.git
synced 2024-10-01 17:21:06 +00:00
371 lines
8 KiB
C++
371 lines
8 KiB
C++
#include "core/arm/interpreter/armdefs.h"
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/* mmu cache init
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*
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* @cache_t :cache_t to init
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* @width :cache line width in byte
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* @way :way of each cache set
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* @set :cache set num
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*
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* $ -1: error
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* 0: sucess
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*/
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int
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mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode)
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{
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int i, j;
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cache_set_t *sets;
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cache_line_t *lines;
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/*alloc cache set */
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sets = NULL;
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lines = NULL;
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//fprintf(stderr, "mmu_cache_init: mallloc beg size %d,sets 0x%x\n", sizeof(cache_set_t) * set,sets);
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//exit(-1);
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sets = (cache_set_t *) malloc (sizeof (cache_set_t) * set);
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if (sets == NULL) {
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ERROR_LOG(ARM11, "set malloc size %d\n", sizeof (cache_set_t) * set);
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goto sets_error;
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}
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//fprintf(stderr, "mmu_cache_init: mallloc end sets 0x%x\n", sets);
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cache_t->sets = sets;
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/*init cache set */
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for (i = 0; i < set; i++) {
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/*alloc cache line */
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lines = (cache_line_t *) malloc (sizeof (cache_line_t) * way);
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if (lines == NULL) {
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ERROR_LOG(ARM11, "line malloc size %d\n",
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sizeof (cache_line_t) * way);
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goto lines_error;
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}
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/*init cache line */
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for (j = 0; j < way; j++) {
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lines[j].tag = 0; //invalid
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lines[j].data = (ARMword *) malloc (width);
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if (lines[j].data == NULL) {
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ERROR_LOG(ARM11, "data alloc size %d\n", width);
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goto data_error;
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}
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}
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sets[i].lines = lines;
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sets[i].cycle = 0;
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}
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cache_t->width = width;
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cache_t->set = set;
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cache_t->way = way;
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cache_t->w_mode = w_mode;
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return 0;
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data_error:
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/*free data */
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while (j-- > 0)
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free (lines[j].data);
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/*free data error line */
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free (lines);
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lines_error:
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/*free lines already alloced */
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while (i-- > 0) {
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for (j = 0; j < way; j++)
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free (sets[i].lines[j].data);
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free (sets[i].lines);
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}
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/*free sets */
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free (sets);
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sets_error:
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return -1;
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};
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/* free a cache_t's inner data, the ptr self is not freed,
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* when needed do like below:
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* mmu_cache_exit(cache);
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* free(cache_t);
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*
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* @cache_t : the cache_t to free
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*/
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void
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mmu_cache_exit (cache_s * cache_t)
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{
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int i, j;
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cache_set_t *sets, *set;
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cache_line_t *lines, *line;
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/*free all set */
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sets = cache_t->sets;
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for (set = sets, i = 0; i < cache_t->set; i++, set++) {
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/*free all line */
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lines = set->lines;
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for (line = lines, j = 0; j < cache_t->way; j++, line++)
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free (line->data);
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free (lines);
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}
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free (sets);
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}
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/* mmu cache search
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*
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* @state :ARMul_State
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* @cache_t :cache_t to search
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* @va :virtual address
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*
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* $ NULL: no cache match
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* cache :cache matched
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*/
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cache_line_t *
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mmu_cache_search (ARMul_State * state, cache_s * cache_t, ARMword va)
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{
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int i;
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int set = va_cache_set (va, cache_t);
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ARMword tag = va_cache_align (va, cache_t);
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cache_line_t *cache;
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cache_set_t *cache_set = cache_t->sets + set;
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for (i = 0, cache = cache_set->lines; i < cache_t->way; i++, cache++) {
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if ((cache->tag & TAG_VALID_FLAG)
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&& (tag == va_cache_align (cache->tag, cache_t)))
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return cache;
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}
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return NULL;
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}
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/* mmu cache search by set/index
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*
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* @state :ARMul_State
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* @cache_t :cache_t to search
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* @index :set/index value.
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*
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* $ NULL: no cache match
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* cache :cache matched
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*/
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cache_line_t *
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mmu_cache_search_by_index (ARMul_State * state, cache_s * cache_t,
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ARMword index)
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{
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int way = cache_t->way;
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int set_v = index_cache_set (index, cache_t);
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int i = 0, index_v = 0;
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cache_set_t *set;
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while ((way >>= 1) >= 1)
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i++;
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index_v = index >> (32 - i);
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set = cache_t->sets + set_v;
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return set->lines + index_v;
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}
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/* mmu cache alloc
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*
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* @state :ARMul_State
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* @cache_t :cache_t to alloc from
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* @va :virtual address that require cache alloc, need not cache aligned
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* @pa :physical address of va
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*
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* $ cache_alloced, always alloc OK
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*/
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cache_line_t *
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mmu_cache_alloc (ARMul_State * state, cache_s * cache_t, ARMword va,
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ARMword pa)
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{
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cache_line_t *cache;
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cache_set_t *set;
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int i;
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va = va_cache_align (va, cache_t);
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pa = va_cache_align (pa, cache_t);
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set = &cache_t->sets[va_cache_set (va, cache_t)];
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/*robin-round */
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cache = &set->lines[set->cycle++];
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if (set->cycle == cache_t->way)
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set->cycle = 0;
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if (cache_t->w_mode == CACHE_WRITE_BACK) {
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ARMword t;
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/*if cache valid, try to write back */
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if (cache->tag & TAG_VALID_FLAG) {
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mmu_cache_write_back (state, cache_t, cache);
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}
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/*read in cache_line */
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t = pa;
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for (i = 0; i < (cache_t->width >> WORD_SHT);
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i++, t += WORD_SIZE) {
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//cache->data[i] = mem_read_word (state, t);
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bus_read(32, t, &cache->data[i]);
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}
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}
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/*store tag and pa */
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cache->tag = va | TAG_VALID_FLAG;
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cache->pa = pa;
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return cache;
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};
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/* mmu_cache_write_back write cache data to memory
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* @state
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* @cache_t :cache_t of the cache line
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* @cache : cache line
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*/
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void
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mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
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cache_line_t * cache)
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{
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ARMword pa = cache->pa;
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int nw = cache_t->width >> WORD_SHT;
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ARMword *data = cache->data;
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int i;
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int t0, t1, t2;
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if ((cache->tag & 1) == 0)
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return;
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switch (cache->
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tag & ~1 & (TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY)) {
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case 0:
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return;
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case TAG_FIRST_HALF_DIRTY:
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nw /= 2;
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break;
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case TAG_LAST_HALF_DIRTY:
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nw /= 2;
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pa += nw << WORD_SHT;
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data += nw;
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break;
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case TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY:
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break;
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}
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for (i = 0; i < nw; i++, data++, pa += WORD_SIZE)
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//mem_write_word (state, pa, *data);
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bus_write(32, pa, *data);
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cache->tag &= ~(TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY);
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};
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/* mmu_cache_clean: clean a cache of va in cache_t
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*
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* @state :ARMul_State
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* @cache_t :cache_t to clean
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* @va :virtaul address
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*/
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void
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mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va)
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{
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cache_line_t *cache;
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cache = mmu_cache_search (state, cache_t, va);
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if (cache)
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mmu_cache_write_back (state, cache_t, cache);
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}
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/* mmu_cache_clean_by_index: clean a cache by set/index format value
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*
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* @state :ARMul_State
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* @cache_t :cache_t to clean
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* @va :set/index format value
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*/
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void
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mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
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ARMword index)
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{
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cache_line_t *cache;
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cache = mmu_cache_search_by_index (state, cache_t, index);
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if (cache)
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mmu_cache_write_back (state, cache_t, cache);
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}
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/* mmu_cache_invalidate : invalidate a cache of va
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*
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* @state :ARMul_State
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* @cache_t :cache_t to invalid
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* @va :virt_addr to invalid
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*/
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void
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mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va)
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{
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cache_line_t *cache;
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cache = mmu_cache_search (state, cache_t, va);
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if (cache) {
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mmu_cache_write_back (state, cache_t, cache);
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cache->tag = 0;
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}
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}
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/* mmu_cache_invalidate_by_index : invalidate a cache by index format
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*
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* @state :ARMul_State
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* @cache_t :cache_t to invalid
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* @index :set/index data
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*/
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void
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mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
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ARMword index)
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{
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cache_line_t *cache;
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cache = mmu_cache_search_by_index (state, cache_t, index);
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if (cache) {
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mmu_cache_write_back (state, cache_t, cache);
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cache->tag = 0;
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}
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}
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/* mmu_cache_invalidate_all
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*
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* @state:
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* @cache_t
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* */
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void
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mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t)
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{
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int i, j;
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cache_set_t *set;
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cache_line_t *cache;
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set = cache_t->sets;
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for (i = 0; i < cache_t->set; i++, set++) {
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cache = set->lines;
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for (j = 0; j < cache_t->way; j++, cache++) {
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mmu_cache_write_back (state, cache_t, cache);
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cache->tag = 0;
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}
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}
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};
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void
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mmu_cache_soft_flush (ARMul_State * state, cache_s * cache_t, ARMword pa)
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{
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ARMword set, way;
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cache_line_t *cache;
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pa = (pa / cache_t->width);
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way = pa & (cache_t->way - 1);
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set = (pa / cache_t->way) & (cache_t->set - 1);
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cache = &cache_t->sets[set].lines[way];
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mmu_cache_write_back (state, cache_t, cache);
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cache->tag = 0;
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}
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cache_line_t* mmu_cache_dirty_cache(ARMul_State *state,cache_s *cache){
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int i;
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int j;
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cache_line_t *cache_line = NULL;
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cache_set_t *cache_set = cache->sets;
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int sets = cache->set;
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for (i = 0; i < sets; i++){
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for(j = 0,cache_line = &cache_set[i].lines[0]; j < cache->way; j++,cache_line++){
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if((cache_line->tag & TAG_FIRST_HALF_DIRTY) || (cache_line->tag & TAG_LAST_HALF_DIRTY))
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return cache_line;
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}
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}
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return NULL;
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}
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