ChocolArm64/State/PState.cs

using System;

namespace ChocolArm64.State
{
    [Flags]
    enum PState
    {
        TBit = 5,
        EBit = 9,

        VBit = 28,
        CBit = 29,
        ZBit = 30,
        NBit = 31,

        TMask = 1 << TBit,
        EMask = 1 << EBit,

        VMask = 1 << VBit,
        CMask = 1 << CBit,
        ZMask = 1 << ZBit,
        NMask = 1 << NBit
    }
}
Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 20:09:23 +00:00			`using System;`

			`namespace ChocolArm64.State`
			`{`
			`[Flags]`
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) * Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment 2018-10-31 01:43:02 +00:00			`enum PState`
Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 20:09:23 +00:00			`{`
Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 2019-01-25 01:59:53 +00:00			`TBit = 5,`
Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 2019-01-29 16:06:11 +00:00			`EBit = 9,`
Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 2019-01-25 01:59:53 +00:00
Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 20:09:23 +00:00			`VBit = 28,`
			`CBit = 29,`
			`ZBit = 30,`
			`NBit = 31,`

Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 2019-01-29 16:06:11 +00:00			`TMask = 1 << TBit,`
			`EMask = 1 << EBit,`
Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 2019-01-25 01:59:53 +00:00
Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 2019-01-29 16:06:11 +00:00			`VMask = 1 << VBit,`
			`CMask = 1 << CBit,`
			`ZMask = 1 << ZBit,`
			`NMask = 1 << NBit`
Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 20:09:23 +00:00			`}`
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) * Update CpuTest.cs * Update CpuTestSimd.cs * Superseded. * Update AInstEmitSimdCvt.cs * Update ASoftFloat.cs * Nit. * Update PackageReferences. * Update AInstEmitSimdArithmetic.cs * Update AVectorHelper.cs * Update ASoftFloat.cs * Update ASoftFallback.cs * Update AThreadState.cs * Create FPType.cs * Create FPExc.cs * Create FPCR.cs * Create FPSR.cs * Update ARoundMode.cs * Update APState.cs * Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover. * Nits. 2018-10-23 14:12:45 +00:00			`}`