12 commits

Author	SHA1	Message	Date
riperiperi	05ef572474	Faster soft implementation of smulh and umulh (#134) ... * Faster soft implementation of smulh and umulh * smulh: Fixed mul with 0 acting like it had a negative result. * Use compliment for negative smulh result.	2018-06-13 10:55:45 -03:00
gdkchan	1aa96453ef	Add intrinsics support (#121) ... * Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake	2018-05-11 20:10:27 -03:00
LDj3SNuD	966f6b7203	Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) ... * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs	2018-04-25 23:20:22 -03:00
MS-DOS1999	b0368079fb	Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)	2018-04-19 00:22:12 -03:00
gdkchan	2afc12c4a7	[CPU] Fix CNT instruction	2018-04-10 20:58:32 -03:00
LDj3SNuD	eca2d19d8d	Add Cls Instruction. (#67) ... * Update AInstEmitAlu.cs * Update ASoftFallback.cs * Update AOpCodeTable.cs	2018-03-23 22:06:05 -03:00
gdkchan	70f8db413b	Fix crc32 instruction with size greater than a byte	2018-03-15 18:14:22 -03:00
gdkchan	d3ec30ec32	Remove unused function from CPU	2018-03-14 00:57:07 -03:00
gdkchan	bb0a2aa0f1	Add CRC32 instruction and SLI (vector)	2018-03-14 00:12:05 -03:00
gdkchan	6dd9cdf337	Fix REV64 (vector) instruction	2018-03-02 20:24:16 -03:00
gdkchan	7e68a890a1	Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) instructions, fix for NvFlinger sometimes missing free buffers	2018-02-24 11:19:28 -03:00
emmauss	7601c05662	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00