LDj3SNuD
5ffeeaed02
Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. ( #480 )
...
* Update AILEmitterCtx.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdShift.cs
2018-10-25 19:10:41 -03:00
LDj3SNuD
9533b338ac
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. ( #449 )
...
* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update ASoftFloat.cs
* Update AOpCodeSimdRegElemF.cs
* Update CpuTestSimdIns.cs
* Update CpuTestSimdRegElem.cs
* Create CpuTestSimdRegElemF.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Superseded Fmul_Se Test. Nit.
* Address PR feedback.
* Address PR feedback.
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update AInstEmitSimdShift.cs
2018-10-13 23:35:16 -03:00
LDj3SNuD
3d16dbe12c
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. ( #409 )
...
* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update CpuTestSimdShImm.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdIns.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00
LDj3SNuD
80836050ef
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. ( #407 )
...
* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update AOpCodeSimdShImm.cs
* Update ABitUtils.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdShImm.cs
* Create CpuTestSimdRegElem.cs
* Address PR feedback.
* Nit.
* Nit.
2018-09-08 14:24:29 -03:00
gdkchan
e64f484521
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits ( #225 )
...
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
* Address PR feedback
* Address PR feedback
* Remove another useless temp var
* nit: Alignment
* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()
* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
gdkchan
bcf4cbf135
CPU fix for the cases using a Mask with shift = 0
2018-03-14 01:59:22 -03:00
gdkchan
bb0a2aa0f1
Add CRC32 instruction and SLI (vector)
2018-03-14 00:12:05 -03:00
gdkchan
f43e430f6c
Fix EmitScalarUnaryOpF and add SSRA (vector)
2018-03-10 00:00:31 -03:00
gdkchan
e182fb74f2
Add SHLL instruction
2018-03-09 23:28:38 -03:00
emmauss
7601c05662
Split main project into core,graphics and chocolarm4 subproject ( #29 )
2018-02-20 17:09:23 -03:00
