ChocolArm64/State
gdkchan 0cda6b3cdf Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table
2019-01-29 13:06:11 -03:00
..
Aarch32Mode.cs Add ARM32 support on the translator (#561) 2019-01-24 23:59:53 -02:00
CpuThreadState.cs Implement some ARM32 memory instructions and CMP (#565) 2019-01-29 13:06:11 -03:00
ExecutionMode.cs Add ARM32 support on the translator (#561) 2019-01-24 23:59:53 -02:00
Fpcr.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
FpExc.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
Fpsr.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
FpType.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
PState.cs Implement some ARM32 memory instructions and CMP (#565) 2019-01-29 13:06:11 -03:00
Register.cs Implement some ARM32 memory instructions and CMP (#565) 2019-01-29 13:06:11 -03:00
RegisterAlias.cs Add ARM32 support on the translator (#561) 2019-01-24 23:59:53 -02:00
RegisterSize.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
RegisterType.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00
RoundMode.cs Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-30 22:43:02 -03:00