A C# ARM64 emulator that works translating ARM code to CIL

arm64csharpdotnetdotnet-coreemulation

LDj3SNuD 65c490f350 Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) ... * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimdArithmetic.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs		2018-04-08 16:08:57 -03:00
Decoder	[CPU] Fix CBZ/CBNZ with 32 bits operands	2018-04-06 17:22:26 -03:00
Events
Exceptions
Instruction	Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)	2018-04-08 16:08:57 -03:00
Memory	Improvements to audout (#58)	2018-03-15 21:06:24 -03:00
State	Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count	2018-03-13 21:24:32 -03:00
Translation	Fix 32-bits extended register instructions with 64-bits extensions	2018-03-30 23:32:06 -03:00
ABitUtils.cs
AOpCodeTable.cs	Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)	2018-04-08 16:08:57 -03:00
AOptimizations.cs	Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks	2018-03-10 20:39:16 -03:00
AThread.cs	Allow more than one process, free resources on process dispose, implement SvcExitThread	2018-03-12 01:14:12 -03:00
ATranslatedSub.cs	Improve CPU initial translation speeds (#50)	2018-03-04 14:09:59 -03:00
ATranslatedSubType.cs	Improve CPU initial translation speeds (#50)	2018-03-04 14:09:59 -03:00
ATranslator.cs	HashSet is not thread safe, hopefully this fixes the CPU issue where it throws a exception on Add	2018-04-04 18:17:37 -03:00
ChocolArm64.csproj