Ryujinx/ChocolArm64/Decoders/OpCode32MemImm.cs

using ChocolArm64.Instructions;

namespace ChocolArm64.Decoders
{
    class OpCode32MemImm : OpCode32Mem
    {
        public OpCode32MemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
        {
            Imm = opCode & 0xfff;
        }
    }
}
Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 2019-01-29 16:06:11 +00:00			`using ChocolArm64.Instructions;`

			`namespace ChocolArm64.Decoders`
			`{`
			`class OpCode32MemImm : OpCode32Mem`
			`{`
			`public OpCode32MemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)`
			`{`
			`Imm = opCode & 0xfff;`
			`}`
			`}`
			`}`