Ryujinx/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs

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using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdRegElem : AOpCodeSimdReg
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{
public int Index { get; private set; }
public AOpCodeSimdRegElem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
switch (Size)
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{
case 1:
Index = (OpCode >> 21) & 1 |
(OpCode >> 10) & 2 |
(OpCode >> 18) & 4;
Rm &= 0xf;
break;
case 2:
Index = (OpCode >> 21) & 1 |
(OpCode >> 10) & 2;
break;
default: Emitter = AInstEmit.Und; return;
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}
}
}
}