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Implement Zip1, Zip2 (#25)
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Ryujinx.Tests/Cpu/CpuTestSimdMove.cs
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45
Ryujinx.Tests/Cpu/CpuTestSimdMove.cs
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@ -0,0 +1,45 @@
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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{
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[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
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[TestCase(1u, 0u, 0x2313221221112010ul, 0x2717261625152414ul)]
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[TestCase(0u, 1u, 0x2322131221201110ul, 0x0000000000000000ul)]
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[TestCase(1u, 1u, 0x2322131221201110ul, 0x2726171625241514ul)]
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[TestCase(0u, 2u, 0x2322212013121110ul, 0x0000000000000000ul)]
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[TestCase(1u, 2u, 0x2322212013121110ul, 0x2726252417161514ul)]
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[TestCase(1u, 3u, 0x1716151413121110ul, 0x2726252423222120ul)]
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public void Zip1_V(uint Q, uint size, ulong Result_0, ulong Result_1)
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{
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// ZIP1 V0.<T>, V1.<T>, V2.<T>
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uint Opcode = 0x0E023820 | (Q << 30) | (size << 22);
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AVec V1 = new AVec { X0 = 0x1716151413121110, X1 = 0x1F1E1D1C1B1A1918 };
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AVec V2 = new AVec { X0 = 0x2726252423222120, X1 = 0x2F2E2D2C2B2A2928 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.AreEqual(Result_0, ThreadState.V0.X0);
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Assert.AreEqual(Result_1, ThreadState.V0.X1);
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}
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[TestCase(0u, 0u, 0x2717261625152414ul, 0x0000000000000000ul)]
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[TestCase(1u, 0u, 0x2B1B2A1A29192818ul, 0x2F1F2E1E2D1D2C1Cul)]
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[TestCase(0u, 1u, 0x2726171625241514ul, 0x0000000000000000ul)]
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[TestCase(1u, 1u, 0x2B2A1B1A29281918ul, 0x2F2E1F1E2D2C1D1Cul)]
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[TestCase(0u, 2u, 0x2726252417161514ul, 0x0000000000000000ul)]
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[TestCase(1u, 2u, 0x2B2A29281B1A1918ul, 0x2F2E2D2C1F1E1D1Cul)]
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[TestCase(1u, 3u, 0x1F1E1D1C1B1A1918ul, 0x2F2E2D2C2B2A2928ul)]
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public void Zip2_V(uint Q, uint size, ulong Result_0, ulong Result_1)
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{
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// ZIP2 V0.<T>, V1.<T>, V2.<T>
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uint Opcode = 0x0E027820 | (Q << 30) | (size << 22);
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AVec V1 = new AVec { X0 = 0x1716151413121110, X1 = 0x1F1E1D1C1B1A1918 };
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AVec V2 = new AVec { X0 = 0x2726252423222120, X1 = 0x2F2E2D2C2B2A2928 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.AreEqual(Result_0, ThreadState.V0.X0);
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Assert.AreEqual(Result_1, ThreadState.V0.X1);
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}
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}
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}
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@ -256,6 +256,8 @@ namespace ChocolArm64
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Set("0x001110xx0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg));
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Set("0x001110xx0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd));
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Set("0x001110xx0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg));
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Set("0x001110xx0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg));
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#endregion
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}
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@ -263,6 +263,16 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void Zip1_V(AILEmitterCtx Context)
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{
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EmitVectorZip(Context, Part: 0);
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}
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public static void Zip2_V(AILEmitterCtx Context)
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{
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EmitVectorZip(Context, Part: 1);
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}
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private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
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{
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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@ -295,5 +305,29 @@ namespace ChocolArm64.Instruction
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorZip(AILEmitterCtx Context, int Part)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Half = Elems >> 1;
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for (int Index = 0; Index < Elems; Index++)
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{
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int Elem = Part * Half + (Index >> 1);
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EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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}
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