mirror of
https://github.com/Ryujinx/Ryujinx.git
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ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as short-hands for `F+VL` and `F+VL+DQ`. * ARMeilleure: Add initial support for EVEX instruction encoding Does not implement rounding, or exception controls. * ARMeilleure: Add `X86Vpternlogd` Accelerates the vector-`Not` instruction. * ARMeilleure: Add check for `OSXSAVE` for AVX{2,512} * ARMeilleure: Add check for `XCR0` flags Add XCR0 register checks for AVX and AVX512F, following the guidelines from section 14.3 and 15.2 from the Intel Architecture Software Developer's Manual. * ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting * ARMeilleure: Move XCR0 procedure to GetXcr0Eax * ARMeilleure: Add `XCR0` to `FeatureInfo` structure * ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly Avoids an additional allocation * ARMeilleure: Formatting fixes * ARMeilleure: Fix EVEX encoding src2 register index > Just like in VEX prefix, vvvv is provided in inverted form. * ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I` Passes unit tests, verified instruction utilization * ARMeilleure: Fix EVEX register operand designations Operand 2 was being sourced improperly. EVEX encoded instructions source their operands like so: Operand 1: ModRM:reg Operand 2: EVEX.vvvvv Operand 3: ModRM:r/m Operand 4: Imm This fixes the improper register designations when emitting vpternlog. Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions. * ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V` * ARMeilleure: PTC version bump * ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail * ARMeilleure: Update EVEX encoding comment capitalization
This commit is contained in:
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@ -7,6 +7,7 @@
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<ItemGroup>
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<ProjectReference Include="..\Ryujinx.Common\Ryujinx.Common.csproj" />
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<ProjectReference Include="..\Ryujinx.Memory\Ryujinx.Memory.csproj" />
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</ItemGroup>
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<ItemGroup>
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@ -1034,7 +1034,13 @@ namespace ARMeilleure.CodeGen.X86
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Debug.Assert(opCode != BadOp, "Invalid opcode value.");
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if ((flags & InstructionFlags.Vex) != 0 && HardwareCapabilities.SupportsVexEncoding)
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if ((flags & InstructionFlags.Evex) != 0 && HardwareCapabilities.SupportsEvexEncoding)
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{
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WriteEvexInst(dest, src1, src2, type, flags, opCode);
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opCode &= 0xff;
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}
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else if ((flags & InstructionFlags.Vex) != 0 && HardwareCapabilities.SupportsVexEncoding)
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{
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// In a vex encoding, only one prefix can be active at a time. The active prefix is encoded in the second byte using two bits.
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@ -1153,6 +1159,103 @@ namespace ARMeilleure.CodeGen.X86
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}
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}
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private void WriteEvexInst(
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Operand dest,
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Operand src1,
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Operand src2,
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OperandType type,
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InstructionFlags flags,
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int opCode,
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bool broadcast = false,
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int registerWidth = 128,
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int maskRegisterIdx = 0,
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bool zeroElements = false)
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{
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int op1Idx = dest.GetRegister().Index;
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int op2Idx = src1.GetRegister().Index;
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int op3Idx = src2.GetRegister().Index;
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WriteByte(0x62);
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// P0
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// Extend operand 1 register
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bool r = (op1Idx & 8) == 0;
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// Extend operand 3 register
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bool x = (op3Idx & 16) == 0;
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// Extend operand 3 register
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bool b = (op3Idx & 8) == 0;
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// Extend operand 1 register
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bool rp = (op1Idx & 16) == 0;
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// Escape code index
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byte mm = 0b00;
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switch ((ushort)(opCode >> 8))
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{
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case 0xf00: mm = 0b01; break;
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case 0xf38: mm = 0b10; break;
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case 0xf3a: mm = 0b11; break;
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default: Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); break;
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}
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WriteByte(
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(byte)(
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(r ? 0x80 : 0) |
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(x ? 0x40 : 0) |
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(b ? 0x20 : 0) |
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(rp ? 0x10 : 0) |
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mm));
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// P1
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// Specify 64-bit lane mode
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bool w = Is64Bits(type);
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// Operand 2 register index
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byte vvvv = (byte)(~op2Idx & 0b1111);
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// Opcode prefix
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byte pp = (flags & InstructionFlags.PrefixMask) switch
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{
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InstructionFlags.Prefix66 => 0b01,
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InstructionFlags.PrefixF3 => 0b10,
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InstructionFlags.PrefixF2 => 0b11,
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_ => 0
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};
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WriteByte(
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(byte)(
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(w ? 0x80 : 0) |
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(vvvv << 3) |
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0b100 |
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pp));
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// P2
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// Mask register determines what elements to zero, rather than what elements to merge
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bool z = zeroElements;
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// Specifies register-width
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byte ll = 0b00;
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switch (registerWidth)
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{
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case 128: ll = 0b00; break;
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case 256: ll = 0b01; break;
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case 512: ll = 0b10; break;
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default: Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); break;
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}
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// Embedded broadcast in the case of a memory operand
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bool bcast = broadcast;
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// Extend operand 2 register
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bool vp = (op2Idx & 16) == 0;
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// Mask register index
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Debug.Assert(maskRegisterIdx < 8, $"Invalid mask register index {maskRegisterIdx}.");
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byte aaa = (byte)(maskRegisterIdx & 0b111);
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WriteByte(
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(byte)(
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(z ? 0x80 : 0) |
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(ll << 5) |
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(bcast ? 0x10 : 0) |
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(vp ? 8 : 0) |
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aaa));
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}
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private void WriteCompactInst(Operand operand, int opCode)
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{
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int regIndex = operand.GetRegister().Index;
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@ -20,6 +20,7 @@ namespace ARMeilleure.CodeGen.X86
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Reg8Dest = 1 << 2,
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RexW = 1 << 3,
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Vex = 1 << 4,
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Evex = 1 << 5,
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PrefixBit = 16,
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PrefixMask = 7 << PrefixBit,
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@ -278,6 +279,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Vfnmsub231sd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38bf, InstructionFlags.Vex | InstructionFlags.Prefix66 | InstructionFlags.RexW));
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Add(X86Instruction.Vfnmsub231ss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38bf, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vpblendvb, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a4c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vpternlogd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a25, InstructionFlags.Evex | InstructionFlags.Prefix66));
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Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None));
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Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Xorps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex));
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@ -1,10 +1,14 @@
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using Ryujinx.Memory;
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using System;
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using System.Runtime.InteropServices;
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using System.Runtime.Intrinsics.X86;
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namespace ARMeilleure.CodeGen.X86
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{
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static class HardwareCapabilities
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{
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private delegate uint GetXcr0();
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static HardwareCapabilities()
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{
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if (!X86Base.IsSupported)
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@ -24,6 +28,28 @@ namespace ARMeilleure.CodeGen.X86
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FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
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FeatureInfo7Ecx = (FeatureFlags7Ecx)ecx7;
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}
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Xcr0InfoEax = (Xcr0FlagsEax)GetXcr0Eax();
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}
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private static uint GetXcr0Eax()
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{
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ReadOnlySpan<byte> asmGetXcr0 = new byte[]
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{
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0x31, 0xc9, // xor ecx, ecx
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0xf, 0x01, 0xd0, // xgetbv
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0xc3, // ret
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};
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using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length);
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memGetXcr0.Write(0, asmGetXcr0);
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memGetXcr0.Reprotect(0, (ulong)asmGetXcr0.Length, MemoryPermission.ReadAndExecute);
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var fGetXcr0 = Marshal.GetDelegateForFunctionPointer<GetXcr0>(memGetXcr0.Pointer);
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return fGetXcr0();
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}
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[Flags]
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@ -44,6 +70,7 @@ namespace ARMeilleure.CodeGen.X86
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Sse42 = 1 << 20,
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Popcnt = 1 << 23,
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Aes = 1 << 25,
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Osxsave = 1 << 27,
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Avx = 1 << 28,
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F16c = 1 << 29
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}
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@ -52,7 +79,11 @@ namespace ARMeilleure.CodeGen.X86
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public enum FeatureFlags7Ebx
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{
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Avx2 = 1 << 5,
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Sha = 1 << 29
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Avx512f = 1 << 16,
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Avx512dq = 1 << 17,
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Sha = 1 << 29,
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Avx512bw = 1 << 30,
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Avx512vl = 1 << 31
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}
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[Flags]
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@ -61,10 +92,21 @@ namespace ARMeilleure.CodeGen.X86
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Gfni = 1 << 8,
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}
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[Flags]
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public enum Xcr0FlagsEax
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{
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Sse = 1 << 1,
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YmmHi128 = 1 << 2,
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Opmask = 1 << 5,
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ZmmHi256 = 1 << 6,
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Hi16Zmm = 1 << 7
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}
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public static FeatureFlags1Edx FeatureInfo1Edx { get; }
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public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
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public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
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public static FeatureFlags7Ecx FeatureInfo7Ecx { get; } = 0;
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public static Xcr0FlagsEax Xcr0InfoEax { get; } = 0;
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public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
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public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
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@ -76,8 +118,13 @@ namespace ARMeilleure.CodeGen.X86
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public static bool SupportsSse42 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse42);
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public static bool SupportsPopcnt => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Popcnt);
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public static bool SupportsAesni => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Aes);
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public static bool SupportsAvx => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Avx);
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public static bool SupportsAvx => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Avx | FeatureFlags1Ecx.Osxsave) && Xcr0InfoEax.HasFlag(Xcr0FlagsEax.Sse | Xcr0FlagsEax.YmmHi128);
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public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
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public static bool SupportsAvx512F => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512f) && FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Osxsave)
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&& Xcr0InfoEax.HasFlag(Xcr0FlagsEax.Sse | Xcr0FlagsEax.YmmHi128 | Xcr0FlagsEax.Opmask | Xcr0FlagsEax.ZmmHi256 | Xcr0FlagsEax.Hi16Zmm);
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public static bool SupportsAvx512Vl => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512vl) && SupportsAvx512F;
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public static bool SupportsAvx512Bw => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512bw) && SupportsAvx512F;
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public static bool SupportsAvx512Dq => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx512dq) && SupportsAvx512F;
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public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
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public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
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public static bool SupportsGfni => FeatureInfo7Ecx.HasFlag(FeatureFlags7Ecx.Gfni);
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public static bool ForceLegacySse { get; set; }
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public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse;
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public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse;
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}
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}
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@ -180,6 +180,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(Intrinsic.X86Vfnmadd231ss, new IntrinsicInfo(X86Instruction.Vfnmadd231ss, IntrinsicType.Fma));
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Add(Intrinsic.X86Vfnmsub231sd, new IntrinsicInfo(X86Instruction.Vfnmsub231sd, IntrinsicType.Fma));
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Add(Intrinsic.X86Vfnmsub231ss, new IntrinsicInfo(X86Instruction.Vfnmsub231ss, IntrinsicType.Fma));
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Add(Intrinsic.X86Vpternlogd, new IntrinsicInfo(X86Instruction.Vpternlogd, IntrinsicType.TernaryImm));
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Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary));
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}
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@ -219,6 +219,7 @@ namespace ARMeilleure.CodeGen.X86
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Vfnmsub231sd,
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Vfnmsub231ss,
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Vpblendvb,
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Vpternlogd,
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Xor,
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Xorpd,
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Xorps,
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@ -254,7 +254,22 @@ namespace ARMeilleure.Instructions
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public static void Not_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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if (Optimizations.UseAvx512Ortho)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand res = context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, n, Const(~0b10101010));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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@ -283,6 +298,22 @@ namespace ARMeilleure.Instructions
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64OrnV);
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}
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else if (Optimizations.UseAvx512Ortho)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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Operand n = GetVec(op.Rn);
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Operand m = GetVec(op.Rm);
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Operand res = context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, m, Const(0b11001100 | ~0b10101010));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2)
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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@ -151,6 +151,13 @@ namespace ARMeilleure.Instructions
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{
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InstEmitSimdHelper32Arm64.EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.Arm64OrnV | Intrinsic.Arm64V128, n, m));
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}
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else if (Optimizations.UseAvx512Ortho)
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{
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Vpternlogd, n, m, Const(0b11001100 | ~0b10101010));
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});
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}
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else if (Optimizations.UseSse2)
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{
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Operand mask = context.VectorOne();
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@ -34,7 +34,14 @@ namespace ARMeilleure.Instructions
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public static void Vmvn_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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if (Optimizations.UseAvx512Ortho)
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{
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EmitVectorUnaryOpSimd32(context, (op1) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Vpternlogd, op1, op1, Const(0b01010101));
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});
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (op1) =>
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{
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@ -173,6 +173,7 @@ namespace ARMeilleure.IntermediateRepresentation
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X86Vfnmadd231ss,
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X86Vfnmsub231sd,
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X86Vfnmsub231ss,
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X86Vpternlogd,
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X86Xorpd,
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X86Xorps,
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@ -23,6 +23,10 @@ namespace ARMeilleure
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public static bool UseSse42IfAvailable { get; set; } = true;
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public static bool UsePopCntIfAvailable { get; set; } = true;
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public static bool UseAvxIfAvailable { get; set; } = true;
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public static bool UseAvx512FIfAvailable { get; set; } = true;
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public static bool UseAvx512VlIfAvailable { get; set; } = true;
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public static bool UseAvx512BwIfAvailable { get; set; } = true;
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public static bool UseAvx512DqIfAvailable { get; set; } = true;
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public static bool UseF16cIfAvailable { get; set; } = true;
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public static bool UseFmaIfAvailable { get; set; } = true;
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public static bool UseAesniIfAvailable { get; set; } = true;
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@ -47,11 +51,18 @@ namespace ARMeilleure
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internal static bool UseSse42 => UseSse42IfAvailable && X86HardwareCapabilities.SupportsSse42;
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internal static bool UsePopCnt => UsePopCntIfAvailable && X86HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && X86HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseAvx512F => UseAvx512FIfAvailable && X86HardwareCapabilities.SupportsAvx512F && !ForceLegacySse;
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internal static bool UseAvx512Vl => UseAvx512VlIfAvailable && X86HardwareCapabilities.SupportsAvx512Vl && !ForceLegacySse;
|
||||
internal static bool UseAvx512Bw => UseAvx512BwIfAvailable && X86HardwareCapabilities.SupportsAvx512Bw && !ForceLegacySse;
|
||||
internal static bool UseAvx512Dq => UseAvx512DqIfAvailable && X86HardwareCapabilities.SupportsAvx512Dq && !ForceLegacySse;
|
||||
internal static bool UseF16c => UseF16cIfAvailable && X86HardwareCapabilities.SupportsF16c;
|
||||
internal static bool UseFma => UseFmaIfAvailable && X86HardwareCapabilities.SupportsFma;
|
||||
internal static bool UseAesni => UseAesniIfAvailable && X86HardwareCapabilities.SupportsAesni;
|
||||
internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && X86HardwareCapabilities.SupportsPclmulqdq;
|
||||
internal static bool UseSha => UseShaIfAvailable && X86HardwareCapabilities.SupportsSha;
|
||||
internal static bool UseGfni => UseGfniIfAvailable && X86HardwareCapabilities.SupportsGfni;
|
||||
|
||||
internal static bool UseAvx512Ortho => UseAvx512F && UseAvx512Vl;
|
||||
internal static bool UseAvx512OrthoFloat => UseAvx512Ortho && UseAvx512Dq;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -30,7 +30,7 @@ namespace ARMeilleure.Translation.PTC
|
|||
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
||||
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
||||
|
||||
private const uint InternalVersion = 4484; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
private const uint InternalVersion = 4485; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
|
||||
private const string ActualDir = "0";
|
||||
private const string BackupDir = "1";
|
||||
|
@ -969,6 +969,7 @@ namespace ARMeilleure.Translation.PTC
|
|||
(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap,
|
||||
(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap2,
|
||||
(ulong)Arm64HardwareCapabilities.MacOsFeatureInfo,
|
||||
0,
|
||||
0);
|
||||
}
|
||||
else if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
|
||||
|
@ -977,11 +978,12 @@ namespace ARMeilleure.Translation.PTC
|
|||
(ulong)X86HardwareCapabilities.FeatureInfo1Ecx,
|
||||
(ulong)X86HardwareCapabilities.FeatureInfo1Edx,
|
||||
(ulong)X86HardwareCapabilities.FeatureInfo7Ebx,
|
||||
(ulong)X86HardwareCapabilities.FeatureInfo7Ecx);
|
||||
(ulong)X86HardwareCapabilities.FeatureInfo7Ecx,
|
||||
(ulong)X86HardwareCapabilities.Xcr0InfoEax);
|
||||
}
|
||||
else
|
||||
{
|
||||
return new FeatureInfo(0, 0, 0, 0);
|
||||
return new FeatureInfo(0, 0, 0, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1002,7 +1004,7 @@ namespace ARMeilleure.Translation.PTC
|
|||
return osPlatform;
|
||||
}
|
||||
|
||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 78*/)]
|
||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 86*/)]
|
||||
private struct OuterHeader
|
||||
{
|
||||
public ulong Magic;
|
||||
|
@ -1034,8 +1036,8 @@ namespace ARMeilleure.Translation.PTC
|
|||
}
|
||||
}
|
||||
|
||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 32*/)]
|
||||
private record struct FeatureInfo(ulong FeatureInfo0, ulong FeatureInfo1, ulong FeatureInfo2, ulong FeatureInfo3);
|
||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 40*/)]
|
||||
private record struct FeatureInfo(ulong FeatureInfo0, ulong FeatureInfo1, ulong FeatureInfo2, ulong FeatureInfo3, ulong FeatureInfo4);
|
||||
|
||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)]
|
||||
private struct InnerHeader
|
||||
|
|
Loading…
Reference in a new issue