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https://github.com/Ryujinx/Ryujinx.git
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Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)
* Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
c05600a26b
commit
4518c52c65
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@ -360,6 +360,8 @@ namespace ChocolArm64
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SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<100000011010xxxxxxxxxx", AInstEmit.Sadalp_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<100000001010xxxxxxxxxx", AInstEmit.Saddlp_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
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SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
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SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
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@ -429,7 +431,9 @@ namespace ChocolArm64
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SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<100000011010xxxxxxxxxx", AInstEmit.Uadalp_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<100000001010xxxxxxxxxx", AInstEmit.Uaddlp_V, typeof(AOpCodeSimd));
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SetA64("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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SetA64("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg));
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@ -158,6 +158,41 @@ namespace ChocolArm64.Instruction
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Context.MarkLabel(LblTrue);
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}
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private static void EmitAddLongPairwise(AILEmitterCtx Context, bool Signed, bool Accumulate)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Words = Op.GetBitsCount() >> 4;
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int Pairs = Words >> Op.Size;
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for (int Index = 0; Index < Pairs; Index++)
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{
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int Idx = Index << 1;
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EmitVectorExtract(Context, Op.Rn, Idx, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rn, Idx + 1, Op.Size, Signed);
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Context.Emit(OpCodes.Add);
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if (Accumulate)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size + 1, Signed);
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Context.Emit(OpCodes.Add);
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}
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EmitVectorInsertTmp(Context, Index, Op.Size + 1);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -992,6 +1027,16 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Sadalp_V(AILEmitterCtx Context)
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{
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EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
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}
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public static void Saddlp_V(AILEmitterCtx Context)
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{
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EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
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}
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public static void Saddw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
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@ -1213,11 +1258,21 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Uadalp_V(AILEmitterCtx Context)
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{
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EmitAddLongPairwise(Context, Signed: false, Accumulate: true);
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}
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public static void Uaddl_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Uaddlp_V(AILEmitterCtx Context)
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{
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EmitAddLongPairwise(Context, Signed: false, Accumulate: false);
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}
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public static void Uaddlv_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -1137,6 +1137,114 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("SADALP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Sadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
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{
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uint Opcode = 0x0E206800; // SADALP V0.4H, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SADALP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Sadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
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{
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uint Opcode = 0x4E206800; // SADALP V0.8H, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Saddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
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{
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uint Opcode = 0x0E202800; // SADDLP V0.4H, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Saddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
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{
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uint Opcode = 0x4E202800; // SADDLP V0.8H, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SQABS <V><d>, <V><n>")]
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public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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@ -1602,6 +1710,114 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("UADALP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Uadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
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{
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uint Opcode = 0x2E206800; // UADALP V0.4H, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("UADALP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Uadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
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{
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uint Opcode = 0x6E206800; // UADALP V0.8H, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("UADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Uaddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B4H, 4H2S, 2S1D>
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{
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uint Opcode = 0x2E202800; // UADDLP V0.4H, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("UADDLP <Vd>.<Ta>, <Vn>.<Tb>")]
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public void Uaddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H, 8H4S, 4S2D>
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{
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uint Opcode = 0x6E202800; // UADDLP V0.8H, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
|
||||
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
|
|||
|
|
@ -3060,6 +3060,90 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// sadalp_advsimd.html
|
||||
public static void Sadalp_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool op = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / (2 * esize);
|
||||
|
||||
bool acc = (op == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand = V(datasize, n);
|
||||
Bits sum;
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
|
||||
Bits result = (acc ? V(datasize, d) : Zeros(datasize));
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned);
|
||||
op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned);
|
||||
|
||||
sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0);
|
||||
|
||||
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// saddlp_advsimd.html
|
||||
public static void Saddlp_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool op = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / (2 * esize);
|
||||
|
||||
bool acc = (op == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand = V(datasize, n);
|
||||
Bits sum;
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
|
||||
Bits result = (acc ? V(datasize, d) : Zeros(datasize));
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned);
|
||||
op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned);
|
||||
|
||||
sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0);
|
||||
|
||||
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqabs_advsimd.html#SQABS_asisdmisc_R
|
||||
public static void Sqabs_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -3522,6 +3606,90 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// uadalp_advsimd.html
|
||||
public static void Uadalp_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
const bool op = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / (2 * esize);
|
||||
|
||||
bool acc = (op == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand = V(datasize, n);
|
||||
Bits sum;
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
|
||||
Bits result = (acc ? V(datasize, d) : Zeros(datasize));
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned);
|
||||
op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned);
|
||||
|
||||
sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0);
|
||||
|
||||
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uaddlp_advsimd.html
|
||||
public static void Uaddlp_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
const bool op = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / (2 * esize);
|
||||
|
||||
bool acc = (op == true);
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand = V(datasize, n);
|
||||
Bits sum;
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
|
||||
Bits result = (acc ? V(datasize, d) : Zeros(datasize));
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned);
|
||||
op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned);
|
||||
|
||||
sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0);
|
||||
|
||||
Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqxtn_advsimd.html#UQXTN_asisdmisc_N
|
||||
public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue