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https://github.com/Ryujinx/Ryujinx.git
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Add SHRN instruction, and fix ADDV
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f68696dc4a
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@ -219,14 +219,17 @@ namespace ChocolArm64
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Set("0x0011100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_V, typeof(AOpCodeSimd));
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Set("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
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Set("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
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Set("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
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Set("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
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Set("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
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Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
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Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
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Set("0x0011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
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Set("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__V, typeof(AOpCodeSimdMemMs));
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Set("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__V, typeof(AOpCodeSimdMemMs));
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Set("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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Set("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
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Set("0x00110100000000xx0xxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
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Set("0x001101100xxxxxxx0xxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
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Set("xx10110xx0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Stp, typeof(AOpCodeSimdMemPair));
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Set("xx111100x00xxxxxxxxx00xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
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Set("xx111100x00xxxxxxxxx01xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm));
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@ -293,7 +296,7 @@ namespace ChocolArm64
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//The < means that we should never have ALL bits with the '<' set.
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//So, when the encoding has <<, it means that 00, 01, and 10 are valid,
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//but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on...
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//For >, the invalid value is zero. So, for << 01, 10 and 11 are valid,
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//For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid,
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//but 00 isn't.
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switch (Encoding[Index])
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{
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@ -273,6 +273,13 @@ namespace ChocolArm64.Instruction
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EmitVectorImmBinaryZx(Context, OpCodes.Shl, Op.Imm - (8 << Op.Size));
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}
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public static void Shrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorImmNarrowBinaryZx(Context, OpCodes.Shr_Un, (8 << (Op.Size + 1)) - Op.Imm);
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}
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public static void Smax_V(AILEmitterCtx Context) => EmitVectorSmax(Context);
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public static void Smin_V(AILEmitterCtx Context) => EmitVectorSmin(Context);
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@ -300,7 +307,8 @@ namespace ChocolArm64.Instruction
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EmitVectorImmBinarySx(Context, OpCodes.Shr, (8 << (Op.Size + 1)) - Op.Imm);
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}
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public static void St__V(AILEmitterCtx Context) => EmitSimdMemMs(Context, IsLoad: false);
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public static void St__Vms(AILEmitterCtx Context) => EmitSimdMemMs(Context, IsLoad: false);
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public static void St__Vss(AILEmitterCtx Context) => EmitSimdMemSs(Context, IsLoad: false);
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public static void Sub_V(AILEmitterCtx Context) => EmitVectorBinaryZx(Context, OpCodes.Sub);
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@ -622,7 +630,7 @@ namespace ChocolArm64.Instruction
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for (int Index = 1; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Op.Size, Index);
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.Emit(OpCodes.Add);
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}
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@ -986,10 +994,6 @@ namespace ChocolArm64.Instruction
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Op.Size);
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if (Opers.HasFlag(OperFlags.Rd))
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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@ -1007,9 +1011,7 @@ namespace ChocolArm64.Instruction
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Emit();
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.InsertVec));
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Context.EmitStvec(Op.Rd);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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@ -1018,27 +1020,27 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorImmBinarySx(AILEmitterCtx Context, OpCode ILOp, long Imm)
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private static void EmitVectorImmBinarySx(AILEmitterCtx Context, OpCode ILOp, int Imm)
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{
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EmitVectorImmBinarySx(Context, () => Context.Emit(ILOp), Imm);
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}
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private static void EmitVectorImmBinaryZx(AILEmitterCtx Context, OpCode ILOp, long Imm)
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private static void EmitVectorImmBinaryZx(AILEmitterCtx Context, OpCode ILOp, int Imm)
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{
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EmitVectorImmBinaryZx(Context, () => Context.Emit(ILOp), Imm);
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}
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private static void EmitVectorImmBinarySx(AILEmitterCtx Context, Action Emit, long Imm)
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private static void EmitVectorImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorImmBinaryOp(Context, Emit, Imm, true);
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}
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private static void EmitVectorImmBinaryZx(AILEmitterCtx Context, Action Emit, long Imm)
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private static void EmitVectorImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorImmBinaryOp(Context, Emit, Imm, false);
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}
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private static void EmitVectorImmBinaryOp(AILEmitterCtx Context, Action Emit, long Imm, bool Signed)
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private static void EmitVectorImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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@ -1046,19 +1048,13 @@ namespace ChocolArm64.Instruction
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Op.Size);
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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Context.EmitLdc_I8(Imm);
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Context.EmitLdc_I4(Imm);
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Emit();
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.InsertVec));
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Context.EmitStvec(Op.Rd);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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@ -1067,6 +1063,56 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorImmNarrowBinarySx(AILEmitterCtx Context, OpCode ILOp, int Imm)
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{
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EmitVectorImmNarrowBinarySx(Context, () => Context.Emit(ILOp), Imm);
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}
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private static void EmitVectorImmNarrowBinaryZx(AILEmitterCtx Context, OpCode ILOp, int Imm)
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{
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EmitVectorImmNarrowBinaryZx(Context, () => Context.Emit(ILOp), Imm);
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}
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private static void EmitVectorImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorImmNarrowBinaryOp(Context, Emit, Imm, true);
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}
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private static void EmitVectorImmNarrowBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorImmNarrowBinaryOp(Context, Emit, Imm, false);
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}
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private static void EmitVectorImmNarrowBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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if (Op.Size < 0 || Op.Size > 2)
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{
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throw new InvalidOperationException(Op.Size.ToString());
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}
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
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Context.EmitLdc_I4(Imm);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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}
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorCmp(AILEmitterCtx Context, OpCode ILOp)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -1141,6 +1187,11 @@ namespace ChocolArm64.Instruction
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private static void EmitVectorExtract(AILEmitterCtx Context, int Reg, int Index, int Size, bool Signed)
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{
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if (Size < 0 || Size > 3)
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Reg);
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@ -1185,6 +1236,11 @@ namespace ChocolArm64.Instruction
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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if (Size < 0 || Size > 3)
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Size);
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@ -1196,6 +1252,11 @@ namespace ChocolArm64.Instruction
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size, long Value)
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{
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if (Size < 0 || Size > 3)
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Size);
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@ -62,10 +62,12 @@ namespace Ryujinx.OsHle.Ipc
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{ ( "time:u", 1), Service.TimeGetStandardNetworkSystemClock },
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{ ( "time:u", 2), Service.TimeGetStandardSteadyClock },
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{ ( "time:u", 3), Service.TimeGetTimeZoneService },
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{ ( "time:u", 4), Service.TimeGetStandardLocalSystemClock },
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{ ( "time:s", 0), Service.TimeGetStandardUserSystemClock },
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{ ( "time:s", 1), Service.TimeGetStandardNetworkSystemClock },
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{ ( "time:s", 2), Service.TimeGetStandardSteadyClock },
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{ ( "time:s", 3), Service.TimeGetTimeZoneService },
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{ ( "time:s", 4), Service.TimeGetStandardLocalSystemClock },
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{ ( "vi:m", 2), Service.ViGetDisplayService },
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};
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@ -12,16 +12,28 @@ namespace Ryujinx.OsHle.Objects.Time
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private static DateTime Epoch = new DateTime(1970, 1, 1, 0, 0, 0, DateTimeKind.Utc);
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public ISystemClock()
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private SystemClockType ClockType;
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public ISystemClock(SystemClockType ClockType)
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{
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m_Commands = new Dictionary<int, ServiceProcessRequest>()
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{
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{ 0, GetCurrentTime }
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};
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this.ClockType = ClockType;
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}
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public long GetCurrentTime(ServiceCtx Context)
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{
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DateTime CurrentTime = DateTime.Now;
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if (ClockType == SystemClockType.Standard ||
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ClockType == SystemClockType.Network)
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{
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CurrentTime = CurrentTime.ToUniversalTime();
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}
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Context.ResponseData.Write((long)(DateTime.Now - Epoch).TotalSeconds);
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return 0;
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9
Ryujinx/OsHle/Objects/Time/SystemClockType.cs
Normal file
9
Ryujinx/OsHle/Objects/Time/SystemClockType.cs
Normal file
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@ -0,0 +1,9 @@
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namespace Ryujinx.OsHle.Objects.Time
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{
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enum SystemClockType
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{
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Standard,
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Network,
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Local
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}
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}
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@ -8,14 +8,14 @@ namespace Ryujinx.OsHle.Services
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{
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public static long TimeGetStandardUserSystemClock(ServiceCtx Context)
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{
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MakeObject(Context, new ISystemClock());
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MakeObject(Context, new ISystemClock(SystemClockType.Standard));
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return 0;
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}
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public static long TimeGetStandardNetworkSystemClock(ServiceCtx Context)
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{
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MakeObject(Context, new ISystemClock());
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MakeObject(Context, new ISystemClock(SystemClockType.Network));
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return 0;
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}
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@ -33,5 +33,13 @@ namespace Ryujinx.OsHle.Services
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return 0;
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}
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public static long TimeGetStandardLocalSystemClock(ServiceCtx Context)
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{
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MakeObject(Context, new ISystemClock(SystemClockType.Local));
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return 0;
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}
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}
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}
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