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Fix REV64 (vector) instruction
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parent
829b1b1cc0
commit
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@ -230,7 +230,7 @@ namespace ChocolArm64
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Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
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Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
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Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
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Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
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Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
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Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
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Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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Set("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
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Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
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Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
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Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
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Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
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@ -1,5 +1,6 @@
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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@ -69,12 +70,25 @@ namespace ChocolArm64.Instruction
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public static void Rev64_V(AILEmitterCtx Context)
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public static void Rev64_V(AILEmitterCtx Context)
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{
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{
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Action Emit = () =>
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int RevIndex = Elems - 1;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64));
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EmitVectorExtractZx(Context, Op.Rn, RevIndex--, Op.Size);
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};
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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EmitVectorUnaryOpZx(Context, Emit);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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}
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}
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}
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}
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@ -75,7 +75,7 @@ namespace ChocolArm64.Instruction
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private static ulong ReverseBytes(ulong Value, RevSize Size)
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private static ulong ReverseBytes(ulong Value, RevSize Size)
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{
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{
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Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8);
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Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8);
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if (Size == RevSize.Rev16)
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if (Size == RevSize.Rev16)
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{
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{
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