mirror of
https://github.com/Ryujinx/Ryujinx.git
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68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask.
96 lines
3 KiB
C#
96 lines
3 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Vand_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Pand, Intrinsic.X86Pand);
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, op2));
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}
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}
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public static void Vbif(ArmEmitterContext context)
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{
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EmitBifBit(context, true);
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}
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public static void Vbit(ArmEmitterContext context)
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{
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EmitBifBit(context, false);
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}
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public static void Vbsl(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorTernaryOpSimd32(context, (d, n, m) =>
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{
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
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res = context.AddIntrinsic(Intrinsic.X86Pand, res, d);
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return context.AddIntrinsic(Intrinsic.X86Pxor, res, m);
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});
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}
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else
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{
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EmitVectorTernaryOpZx32(context, (op1, op2, op3) =>
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{
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return context.BitwiseExclusiveOr(
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context.BitwiseAnd(op1,
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context.BitwiseExclusiveOr(op2, op3)), op3);
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});
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}
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}
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public static void Vorr_I(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Por, Intrinsic.X86Por);
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, op2));
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}
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}
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private static void EmitBifBit(ArmEmitterContext context, bool notRm)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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EmitVectorTernaryOpSimd32(context, (d, n, m) =>
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{
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Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, d);
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res = context.AddIntrinsic((notRm) ? Intrinsic.X86Pandn : Intrinsic.X86Pand, m, res);
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return context.AddIntrinsic(Intrinsic.X86Pxor, d, res);
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});
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}
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else
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{
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EmitVectorTernaryOpZx32(context, (d, n, m) =>
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{
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if (notRm)
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{
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m = context.BitwiseNot(m);
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}
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return context.BitwiseExclusiveOr(
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context.BitwiseAnd(m,
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context.BitwiseExclusiveOr(d, n)), d);
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});
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}
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}
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}
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}
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