Ryujinx/Ryujinx/Cpu
2018-02-09 00:26:20 -03:00
..
Decoder Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
Exceptions aloha 2018-02-04 20:08:20 -03:00
Instruction Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
Memory Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
State Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method 2018-02-06 12:15:08 -03:00
Translation Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo 2018-02-06 20:28:32 -03:00
ABitUtils.cs aloha 2018-02-04 20:08:20 -03:00
AOpCodeTable.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AOptimizations.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AThread.cs aloha 2018-02-04 20:08:20 -03:00
ATranslatedSub.cs aloha 2018-02-04 20:08:20 -03:00
ATranslator.cs aloha 2018-02-04 20:08:20 -03:00