mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-07 23:38:39 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
37 lines
1.1 KiB
C#
37 lines
1.1 KiB
C#
using ChocolArm64.Instructions;
|
|
|
|
namespace ChocolArm64.Decoders
|
|
{
|
|
class OpCode32Mem : OpCode32, IOpCode32Mem
|
|
{
|
|
public int Rt { get; private set; }
|
|
public int Rn { get; private set; }
|
|
|
|
public int Imm { get; protected set; }
|
|
|
|
public bool Index { get; private set; }
|
|
public bool Add { get; private set; }
|
|
public bool WBack { get; private set; }
|
|
public bool Unprivileged { get; private set; }
|
|
|
|
public bool IsLoad { get; private set; }
|
|
|
|
public OpCode32Mem(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
|
{
|
|
Rt = (opCode >> 12) & 0xf;
|
|
Rn = (opCode >> 16) & 0xf;
|
|
|
|
bool isLoad = (opCode & (1 << 20)) != 0;
|
|
bool w = (opCode & (1 << 21)) != 0;
|
|
bool u = (opCode & (1 << 23)) != 0;
|
|
bool p = (opCode & (1 << 24)) != 0;
|
|
|
|
Index = p;
|
|
Add = u;
|
|
WBack = !p || w;
|
|
Unprivileged = !p && w;
|
|
|
|
IsLoad = isLoad || inst.Emitter == InstEmit32.Ldrd;
|
|
}
|
|
}
|
|
} |