mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-09 08:08:32 +00:00
98e05ee4b7
* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
27 lines
738 B
C#
27 lines
738 B
C#
using ARMeilleure.State;
|
|
|
|
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem
|
|
{
|
|
public int Rt { get; }
|
|
public int Rn => RegisterAlias.Aarch32Pc;
|
|
|
|
public bool WBack => false;
|
|
public bool IsLoad => true;
|
|
public bool Index => true;
|
|
public bool Add => true;
|
|
|
|
public int Immediate { get; }
|
|
|
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode);
|
|
|
|
public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
Rt = (opCode >> 8) & 7;
|
|
|
|
Immediate = (opCode & 0xff) << 2;
|
|
}
|
|
}
|
|
}
|