Ryujinx/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
LDj3SNuD 04e330cc00
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).

No test provided (i.e. draft).

* Ptc InternalVersion = 1577
2020-10-13 22:41:33 +02:00

18 lines
587 B
C#

namespace ARMeilleure.Decoders
{
class OpCode32SimdRegWide : OpCode32SimdReg
{
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
RegisterSize = RegisterSize.Simd64;
// Subclasses have their own handling of Vx to account for before checking.
if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn))
{
Instruction = InstDescriptor.Undefined;
}
}
}
}