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https://github.com/Ryujinx/Ryujinx.git
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36ec1bc6c0
* Relax block ordering constraints Before `block.Next` had to follow `block.ListNext`, now it does not. Instead `CodeGenerator` will now emit the necessary jump instructions to ensure control flow. This makes control flow and block order modifications easier. It also eliminates some simple cases of redundant branches. * Set PPTC version
431 lines
16 KiB
C#
431 lines
16 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System.Collections.Generic;
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using System.Diagnostics;
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using System.Numerics;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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using static ARMeilleure.IntermediateRepresentation.OperationHelper;
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namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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class HybridAllocator : IRegisterAllocator
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{
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private const int RegistersCount = 16;
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private const int MaxIROperands = 4;
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private struct BlockInfo
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{
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public bool HasCall { get; }
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public int IntFixedRegisters { get; }
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public int VecFixedRegisters { get; }
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public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters)
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{
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HasCall = hasCall;
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IntFixedRegisters = intFixedRegisters;
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VecFixedRegisters = vecFixedRegisters;
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}
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}
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private class LocalInfo
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{
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public int Uses { get; set; }
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public int UseCount { get; set; }
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public bool PreAllocated { get; set; }
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public int Register { get; set; }
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public int SpillOffset { get; set; }
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public int Sequence { get; set; }
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public Operand Temp { get; set; }
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public OperandType Type { get; }
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private int _first;
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private int _last;
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public bool IsBlockLocal => _first == _last;
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public LocalInfo(OperandType type, int uses)
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{
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Uses = uses;
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Type = type;
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_first = -1;
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_last = -1;
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}
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public void SetBlockIndex(int blkIndex)
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{
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if (_first == -1 || blkIndex < _first)
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{
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_first = blkIndex;
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}
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if (_last == -1 || blkIndex > _last)
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{
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_last = blkIndex;
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}
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}
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}
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public AllocationResult RunPass(
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ControlFlowGraph cfg,
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StackAllocator stackAlloc,
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RegisterMasks regMasks)
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{
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int intUsedRegisters = 0;
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int vecUsedRegisters = 0;
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int intFreeRegisters = regMasks.IntAvailableRegisters;
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int vecFreeRegisters = regMasks.VecAvailableRegisters;
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BlockInfo[] blockInfo = new BlockInfo[cfg.Blocks.Count];
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List<LocalInfo> locInfo = new List<LocalInfo>();
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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int intFixedRegisters = 0;
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int vecFixedRegisters = 0;
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bool hasCall = false;
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for (Node node = block.Operations.First; node != null; node = node.ListNext)
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{
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if (node is Operation operation && operation.Instruction == Instruction.Call)
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{
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hasCall = true;
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}
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for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
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{
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Operand source = node.GetSource(srcIndex);
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if (source.Kind == OperandKind.LocalVariable)
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{
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locInfo[source.AsInt32() - 1].SetBlockIndex(block.Index);
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}
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else if (source.Kind == OperandKind.Memory)
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{
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MemoryOperand memOp = (MemoryOperand)source;
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if (memOp.BaseAddress != null)
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{
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locInfo[memOp.BaseAddress.AsInt32() - 1].SetBlockIndex(block.Index);
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}
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if (memOp.Index != null)
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{
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locInfo[memOp.Index.AsInt32() - 1].SetBlockIndex(block.Index);
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}
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}
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}
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for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
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{
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Operand dest = node.GetDestination(dstIndex);
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if (dest.Kind == OperandKind.LocalVariable)
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{
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LocalInfo info;
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if (dest.Value != 0)
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{
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info = locInfo[dest.AsInt32() - 1];
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}
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else
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{
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dest.NumberLocal(locInfo.Count + 1);
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info = new LocalInfo(dest.Type, UsesCount(dest));
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locInfo.Add(info);
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}
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info.SetBlockIndex(block.Index);
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}
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else if (dest.Kind == OperandKind.Register)
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{
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if (dest.Type.IsInteger())
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{
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intFixedRegisters |= 1 << dest.GetRegister().Index;
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}
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else
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{
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vecFixedRegisters |= 1 << dest.GetRegister().Index;
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}
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}
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}
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}
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blockInfo[block.Index] = new BlockInfo(hasCall, intFixedRegisters, vecFixedRegisters);
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}
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int sequence = 0;
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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BlockInfo blkInfo = blockInfo[block.Index];
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int intLocalFreeRegisters = intFreeRegisters & ~blkInfo.IntFixedRegisters;
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int vecLocalFreeRegisters = vecFreeRegisters & ~blkInfo.VecFixedRegisters;
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int intCallerSavedRegisters = blkInfo.HasCall ? regMasks.IntCallerSavedRegisters : 0;
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int vecCallerSavedRegisters = blkInfo.HasCall ? regMasks.VecCallerSavedRegisters : 0;
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int intSpillTempRegisters = SelectSpillTemps(
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intCallerSavedRegisters & ~blkInfo.IntFixedRegisters,
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intLocalFreeRegisters);
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int vecSpillTempRegisters = SelectSpillTemps(
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vecCallerSavedRegisters & ~blkInfo.VecFixedRegisters,
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vecLocalFreeRegisters);
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intLocalFreeRegisters &= ~(intSpillTempRegisters | intCallerSavedRegisters);
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vecLocalFreeRegisters &= ~(vecSpillTempRegisters | vecCallerSavedRegisters);
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for (Node node = block.Operations.First; node != null; node = node.ListNext)
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{
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int intLocalUse = 0;
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int vecLocalUse = 0;
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void AllocateRegister(Operand source, MemoryOperand memOp, int srcIndex)
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{
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LocalInfo info = locInfo[source.AsInt32() - 1];
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info.UseCount++;
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Debug.Assert(info.UseCount <= info.Uses);
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if (info.Register != -1)
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{
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Operand reg = Register(info.Register, source.Type.ToRegisterType(), source.Type);
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if (memOp != null)
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{
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if (srcIndex == 0)
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{
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memOp.BaseAddress = reg;
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}
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else /* if (srcIndex == 1) */
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{
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memOp.Index = reg;
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}
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}
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else
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{
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node.SetSource(srcIndex, reg);
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}
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if (info.UseCount == info.Uses && !info.PreAllocated)
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{
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if (source.Type.IsInteger())
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{
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intLocalFreeRegisters |= 1 << info.Register;
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}
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else
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{
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vecLocalFreeRegisters |= 1 << info.Register;
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}
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}
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}
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else
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{
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Operand temp = info.Temp;
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if (temp == null || info.Sequence != sequence)
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{
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temp = source.Type.IsInteger()
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? GetSpillTemp(source, intSpillTempRegisters, ref intLocalUse)
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: GetSpillTemp(source, vecSpillTempRegisters, ref vecLocalUse);
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info.Sequence = sequence;
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info.Temp = temp;
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}
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if (memOp != null)
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{
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if (srcIndex == 0)
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{
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memOp.BaseAddress = temp;
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}
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else /* if (srcIndex == 1) */
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{
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memOp.Index = temp;
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}
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}
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else
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{
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node.SetSource(srcIndex, temp);
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}
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Operation fillOp = Operation(Instruction.Fill, temp, Const(info.SpillOffset));
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block.Operations.AddBefore(node, fillOp);
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}
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}
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for (int srcIndex = 0; srcIndex < node.SourcesCount; srcIndex++)
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{
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Operand source = node.GetSource(srcIndex);
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if (source.Kind == OperandKind.LocalVariable)
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{
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AllocateRegister(source, null, srcIndex);
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}
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else if (source.Kind == OperandKind.Memory)
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{
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MemoryOperand memOp = (MemoryOperand)source;
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if (memOp.BaseAddress != null)
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{
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AllocateRegister(memOp.BaseAddress, memOp, 0);
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}
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if (memOp.Index != null)
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{
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AllocateRegister(memOp.Index, memOp, 1);
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}
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}
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}
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int intLocalAsg = 0;
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int vecLocalAsg = 0;
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for (int dstIndex = 0; dstIndex < node.DestinationsCount; dstIndex++)
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{
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Operand dest = node.GetDestination(dstIndex);
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if (dest.Kind != OperandKind.LocalVariable)
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{
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continue;
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}
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LocalInfo info = locInfo[dest.AsInt32() - 1];
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if (info.UseCount == 0 && !info.PreAllocated)
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{
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int mask = dest.Type.IsInteger()
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? intLocalFreeRegisters
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: vecLocalFreeRegisters;
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if (info.IsBlockLocal && mask != 0)
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{
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int selectedReg = BitOperations.TrailingZeroCount(mask);
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info.Register = selectedReg;
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if (dest.Type.IsInteger())
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{
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intLocalFreeRegisters &= ~(1 << selectedReg);
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intUsedRegisters |= 1 << selectedReg;
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}
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else
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{
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vecLocalFreeRegisters &= ~(1 << selectedReg);
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vecUsedRegisters |= 1 << selectedReg;
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}
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}
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else
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{
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info.Register = -1;
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info.SpillOffset = stackAlloc.Allocate(dest.Type.GetSizeInBytes());
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}
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}
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info.UseCount++;
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Debug.Assert(info.UseCount <= info.Uses);
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if (info.Register != -1)
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{
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node.SetDestination(dstIndex, Register(info.Register, dest.Type.ToRegisterType(), dest.Type));
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}
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else
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{
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Operand temp = info.Temp;
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if (temp == null || info.Sequence != sequence)
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{
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temp = dest.Type.IsInteger()
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? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg)
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: GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
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info.Sequence = sequence;
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info.Temp = temp;
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}
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node.SetDestination(dstIndex, temp);
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Operation spillOp = Operation(Instruction.Spill, null, Const(info.SpillOffset), temp);
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block.Operations.AddAfter(node, spillOp);
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node = spillOp;
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}
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}
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sequence++;
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intUsedRegisters |= intLocalAsg | intLocalUse;
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vecUsedRegisters |= vecLocalAsg | vecLocalUse;
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}
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}
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return new AllocationResult(intUsedRegisters, vecUsedRegisters, stackAlloc.TotalSize);
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}
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private static int SelectSpillTemps(int mask0, int mask1)
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{
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int selection = 0;
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int count = 0;
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while (count < MaxIROperands && mask0 != 0)
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{
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int mask = mask0 & -mask0;
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selection |= mask;
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mask0 &= ~mask;
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count++;
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}
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while (count < MaxIROperands && mask1 != 0)
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{
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int mask = mask1 & -mask1;
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selection |= mask;
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mask1 &= ~mask;
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count++;
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}
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Debug.Assert(count == MaxIROperands, "No enough registers for spill temps.");
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return selection;
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}
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private static Operand GetSpillTemp(Operand local, int freeMask, ref int useMask)
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{
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int selectedReg = BitOperations.TrailingZeroCount(freeMask & ~useMask);
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useMask |= 1 << selectedReg;
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return Register(selectedReg, local.Type.ToRegisterType(), local.Type);
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}
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private static int UsesCount(Operand local)
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{
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return local.Assignments.Count + local.Uses.Count;
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}
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}
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} |