mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-08 15:48:33 +00:00
5e0f8e8738
* Implement JIT Arm64 backend * PPTC version bump * Address some feedback from Arm64 JIT PR * Address even more PR feedback * Remove unused IsPageAligned function * Sync Qc flag before calls * Fix comment and remove unused enum * Address riperiperi PR feedback * Delete Breakpoint IR instruction that was only implemented for Arm64
790 lines
30 KiB
C#
790 lines
30 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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private static int FlipVdBits(int vd, bool lowBit)
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{
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if (lowBit)
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{
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// Move the low bit to the top.
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return ((vd & 0x1) << 4) | (vd >> 1);
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}
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else
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{
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// Move the high bit to the bottom.
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return ((vd & 0xf) << 1) | (vd >> 4);
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}
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}
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private static Operand EmitSaturateFloatToInt(ArmEmitterContext context, Operand op1, bool unsigned)
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{
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MethodInfo info;
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if (op1.Type == OperandType.FP64)
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{
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info = unsigned
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? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32))
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: typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32));
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}
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else
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{
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info = unsigned
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? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32))
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: typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32));
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}
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return context.Call(info, op1);
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}
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public static void Vcvt_V(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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bool unsigned = (op.Opc & 1) != 0;
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bool toInteger = (op.Opc & 2) != 0;
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OperandType floatSize = (op.Size == 2) ? OperandType.FP32 : OperandType.FP64;
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if (toInteger)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorUnaryOpF32(context, unsigned ? Intrinsic.Arm64FcvtzuV : Intrinsic.Arm64FcvtzsV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41ConvertVector32(context, FPRoundingMode.TowardsZero, !unsigned);
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}
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else
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{
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EmitVectorUnaryOpF32(context, (op1) =>
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{
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return EmitSaturateFloatToInt(context, op1, unsigned);
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});
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}
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}
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else
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (n) =>
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{
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if (unsigned)
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{
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Operand mask = X86GetAllElements(context, 0x47800000);
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Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
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res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
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res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
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Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
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res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
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res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
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return context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
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}
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else
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{
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return context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, n);
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}
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});
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}
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else
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{
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if (unsigned)
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{
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EmitVectorUnaryOpZx32(context, (op1) => EmitFPConvert(context, op1, floatSize, false));
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}
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else
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{
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EmitVectorUnaryOpSx32(context, (op1) => EmitFPConvert(context, op1, floatSize, true));
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}
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}
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}
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}
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public static void Vcvt_FD(ArmEmitterContext context)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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int vm = op.Vm;
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int vd;
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if (op.Size == 3)
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{
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vd = FlipVdBits(op.Vd, false);
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// Double to single.
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Operand fp = ExtractScalar(context, OperandType.FP64, vm);
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Operand res = context.ConvertToFP(OperandType.FP32, fp);
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InsertScalar(context, vd, res);
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}
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else
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{
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vd = FlipVdBits(op.Vd, true);
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// Single to double.
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Operand fp = ExtractScalar(context, OperandType.FP32, vm);
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Operand res = context.ConvertToFP(OperandType.FP64, fp);
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InsertScalar(context, vd, res);
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}
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}
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// VCVT (floating-point to integer, floating-point) | VCVT (integer to floating-point, floating-point).
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public static void Vcvt_FI(ArmEmitterContext context)
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{
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OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp;
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bool toInteger = (op.Opc2 & 0b100) != 0;
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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if (toInteger)
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{
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bool unsigned = (op.Opc2 & 1) == 0;
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bool roundWithFpscr = op.Opc != 1;
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if (!roundWithFpscr && Optimizations.UseAdvSimd)
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{
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bool doubleSize = floatSize == OperandType.FP64;
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if (doubleSize)
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{
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Operand m = GetVecA32(op.Vm >> 1);
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Operand toConvert = InstEmitSimdHelper32Arm64.EmitExtractScalar(context, m, op.Vm, doubleSize);
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Intrinsic inst = (unsigned ? Intrinsic.Arm64FcvtzuGp : Intrinsic.Arm64FcvtzsGp) | Intrinsic.Arm64VDouble;
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Operand asInteger = context.AddIntrinsicInt(inst, toConvert);
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InsertScalar(context, op.Vd, asInteger);
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}
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else
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{
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InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, unsigned ? Intrinsic.Arm64FcvtzuS : Intrinsic.Arm64FcvtzsS);
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}
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}
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else if (!roundWithFpscr && Optimizations.UseSse41)
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{
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EmitSse41ConvertInt32(context, FPRoundingMode.TowardsZero, !unsigned);
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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// TODO: Fast Path.
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if (roundWithFpscr)
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{
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toConvert = EmitRoundByRMode(context, toConvert);
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}
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// Round towards zero.
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Operand asInteger = EmitSaturateFloatToInt(context, toConvert, unsigned);
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InsertScalar(context, op.Vd, asInteger);
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}
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}
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else
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{
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bool unsigned = op.Opc == 0;
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Operand toConvert = ExtractScalar(context, OperandType.I32, op.Vm);
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Operand asFloat = EmitFPConvert(context, toConvert, floatSize, !unsigned);
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InsertScalar(context, op.Vd, asFloat);
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}
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}
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private static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRounding roundMode, Operand n)
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{
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IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
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string name = nameof(Math.Round);
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MethodInfo info = (op.Size & 1) == 0
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? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
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: typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
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return context.Call(info, n, Const((int)roundMode));
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}
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private static FPRoundingMode RMToRoundMode(int rm)
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{
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FPRoundingMode roundMode;
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switch (rm)
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{
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case 0b00:
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roundMode = FPRoundingMode.ToNearestAway;
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break;
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case 0b01:
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roundMode = FPRoundingMode.ToNearest;
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break;
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case 0b10:
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roundMode = FPRoundingMode.TowardsPlusInfinity;
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break;
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case 0b11:
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roundMode = FPRoundingMode.TowardsMinusInfinity;
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break;
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default:
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throw new ArgumentOutOfRangeException(nameof(rm));
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}
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return roundMode;
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}
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// VCVTA/M/N/P (floating-point).
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public static void Vcvt_RM(ArmEmitterContext context)
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{
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OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp; // toInteger == true (opCode<18> == 1 => Opc2<2> == 1).
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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bool unsigned = op.Opc == 0;
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int rm = op.Opc2 & 3;
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Intrinsic inst;
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if (Optimizations.UseAdvSimd)
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{
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if (unsigned)
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{
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inst = rm switch {
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0b00 => Intrinsic.Arm64FcvtauS,
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0b01 => Intrinsic.Arm64FcvtnuS,
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0b10 => Intrinsic.Arm64FcvtpuS,
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0b11 => Intrinsic.Arm64FcvtmuS,
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_ => throw new ArgumentOutOfRangeException(nameof(rm))
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};
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}
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else
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{
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inst = rm switch {
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0b00 => Intrinsic.Arm64FcvtasS,
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0b01 => Intrinsic.Arm64FcvtnsS,
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0b10 => Intrinsic.Arm64FcvtpsS,
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0b11 => Intrinsic.Arm64FcvtmsS,
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_ => throw new ArgumentOutOfRangeException(nameof(rm))
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};
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}
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InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41ConvertInt32(context, RMToRoundMode(rm), !unsigned);
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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switch (rm)
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{
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case 0b00: // Away
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toConvert = EmitRoundMathCall(context, MidpointRounding.AwayFromZero, toConvert);
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break;
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case 0b01: // Nearest
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toConvert = EmitRoundMathCall(context, MidpointRounding.ToEven, toConvert);
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break;
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case 0b10: // Towards positive infinity
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toConvert = EmitUnaryMathCall(context, nameof(Math.Ceiling), toConvert);
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break;
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case 0b11: // Towards negative infinity
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toConvert = EmitUnaryMathCall(context, nameof(Math.Floor), toConvert);
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break;
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}
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Operand asInteger = EmitSaturateFloatToInt(context, toConvert, unsigned);
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InsertScalar(context, op.Vd, asInteger);
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}
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}
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public static void Vcvt_TB(ArmEmitterContext context)
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{
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OpCode32SimdCvtTB op = (OpCode32SimdCvtTB)context.CurrOp;
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if (Optimizations.UseF16c)
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{
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Debug.Assert(!Optimizations.ForceLegacySse);
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if (op.Op)
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{
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Operand res = ExtractScalar(context, op.Size == 1 ? OperandType.FP64 : OperandType.FP32, op.Vm);
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if (op.Size == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), res);
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}
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res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
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res = context.VectorExtract16(res, 0);
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InsertScalar16(context, op.Vd, op.T, res);
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}
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else
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{
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Operand res = context.VectorCreateScalar(ExtractScalar16(context, op.Vm, op.T));
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res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
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if (op.Size == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
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}
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res = context.VectorExtract(op.Size == 1 ? OperandType.I64 : OperandType.I32, res, 0);
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InsertScalar(context, op.Vd, res);
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}
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}
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else
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{
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if (op.Op)
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{
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// Convert to half.
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Operand src = ExtractScalar(context, op.Size == 1 ? OperandType.FP64 : OperandType.FP32, op.Vm);
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MethodInfo method = op.Size == 1
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? typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert))
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: typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert));
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context.StoreToContext();
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Operand res = context.Call(method, src);
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context.LoadFromContext();
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InsertScalar16(context, op.Vd, op.T, res);
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}
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else
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{
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// Convert from half.
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Operand src = ExtractScalar16(context, op.Vm, op.T);
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MethodInfo method = op.Size == 1
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? typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert))
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: typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert));
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context.StoreToContext();
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Operand res = context.Call(method, src);
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context.LoadFromContext();
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InsertScalar(context, op.Vd, res);
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}
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}
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}
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// VRINTA/M/N/P (floating-point).
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public static void Vrint_RM(ArmEmitterContext context)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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OperandType floatSize = op.RegisterSize == RegisterSize.Int64 ? OperandType.FP64 : OperandType.FP32;
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int rm = op.Opc2 & 3;
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if (Optimizations.UseAdvSimd)
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{
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Intrinsic inst = rm switch {
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0b00 => Intrinsic.Arm64FrintaS,
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0b01 => Intrinsic.Arm64FrintnS,
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0b10 => Intrinsic.Arm64FrintpS,
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0b11 => Intrinsic.Arm64FrintmS,
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_ => throw new ArgumentOutOfRangeException(nameof(rm))
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};
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InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst);
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}
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else if (Optimizations.UseSse41)
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{
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EmitScalarUnaryOpSimd32(context, (m) =>
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{
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FPRoundingMode roundMode = RMToRoundMode(rm);
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if (roundMode != FPRoundingMode.ToNearestAway)
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{
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Intrinsic inst = (op.Size & 1) == 0 ? Intrinsic.X86Roundss : Intrinsic.X86Roundsd;
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return context.AddIntrinsic(inst, m, Const(X86GetRoundControl(roundMode)));
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}
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else
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{
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return EmitSse41RoundToNearestWithTiesToAwayOpF(context, m, scalar: true);
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}
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});
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}
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else
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{
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Operand toConvert = ExtractScalar(context, floatSize, op.Vm);
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switch (rm)
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{
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case 0b00: // Away
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toConvert = EmitRoundMathCall(context, MidpointRounding.AwayFromZero, toConvert);
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break;
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case 0b01: // Nearest
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toConvert = EmitRoundMathCall(context, MidpointRounding.ToEven, toConvert);
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break;
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case 0b10: // Towards positive infinity
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toConvert = EmitUnaryMathCall(context, nameof(Math.Ceiling), toConvert);
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break;
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case 0b11: // Towards negative infinity
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toConvert = EmitUnaryMathCall(context, nameof(Math.Floor), toConvert);
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break;
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}
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InsertScalar(context, op.Vd, toConvert);
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}
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}
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// VRINTA (vector).
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public static void Vrinta_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorUnaryOpF32(context, Intrinsic.Arm64FrintaS);
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, m));
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}
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}
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// VRINTM (vector).
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public static void Vrintm_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorUnaryOpF32(context, Intrinsic.Arm64FrintmS);
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsMinusInfinity)));
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});
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Floor), m));
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}
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}
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// VRINTN (vector).
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public static void Vrintn_V(ArmEmitterContext context)
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{
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelper32Arm64.EmitVectorUnaryOpF32(context, Intrinsic.Arm64FrintnS);
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}
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else if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
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});
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.ToEven, m));
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}
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}
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// VRINTP (vector).
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public static void Vrintp_V(ArmEmitterContext context)
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{
|
|
if (Optimizations.UseAdvSimd)
|
|
{
|
|
InstEmitSimdHelper32Arm64.EmitVectorUnaryOpF32(context, Intrinsic.Arm64FrintpS);
|
|
}
|
|
else if (Optimizations.UseSse2)
|
|
{
|
|
EmitVectorUnaryOpSimd32(context, (m) =>
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsPlusInfinity)));
|
|
});
|
|
}
|
|
else
|
|
{
|
|
EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Ceiling), m));
|
|
}
|
|
}
|
|
|
|
// VRINTZ (floating-point).
|
|
public static void Vrint_Z(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
|
|
|
|
if (Optimizations.UseAdvSimd)
|
|
{
|
|
InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, Intrinsic.Arm64FrintzS);
|
|
}
|
|
else if (Optimizations.UseSse2)
|
|
{
|
|
EmitScalarUnaryOpSimd32(context, (m) =>
|
|
{
|
|
Intrinsic inst = (op.Size & 1) == 0 ? Intrinsic.X86Roundss : Intrinsic.X86Roundsd;
|
|
return context.AddIntrinsic(inst, m, Const(X86GetRoundControl(FPRoundingMode.TowardsZero)));
|
|
});
|
|
}
|
|
else
|
|
{
|
|
EmitScalarUnaryOpF32(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Truncate), op1));
|
|
}
|
|
}
|
|
|
|
// VRINTX (floating-point).
|
|
public static void Vrintx_S(ArmEmitterContext context)
|
|
{
|
|
EmitScalarUnaryOpF32(context, (op1) =>
|
|
{
|
|
return EmitRoundByRMode(context, op1);
|
|
});
|
|
}
|
|
|
|
private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, OperandType type, bool signed)
|
|
{
|
|
Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
|
|
|
|
if (signed)
|
|
{
|
|
return context.ConvertToFP(type, value);
|
|
}
|
|
else
|
|
{
|
|
return context.ConvertToFPUI(type, value);
|
|
}
|
|
}
|
|
|
|
private static void EmitSse41ConvertInt32(ArmEmitterContext context, FPRoundingMode roundMode, bool signed)
|
|
{
|
|
// A port of the similar round function in InstEmitSimdCvt.
|
|
OpCode32SimdCvtFI op = (OpCode32SimdCvtFI)context.CurrOp;
|
|
|
|
bool doubleSize = (op.Size & 1) != 0;
|
|
int shift = doubleSize ? 1 : 2;
|
|
Operand n = GetVecA32(op.Vm >> shift);
|
|
n = EmitSwapScalar(context, n, op.Vm, doubleSize);
|
|
|
|
if (!doubleSize)
|
|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
if (roundMode != FPRoundingMode.ToNearestAway)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundss, nRes, Const(X86GetRoundControl(roundMode)));
|
|
}
|
|
else
|
|
{
|
|
nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
|
|
}
|
|
|
|
Operand zero = context.VectorZero();
|
|
|
|
Operand nCmp;
|
|
Operand nIntOrLong2 = default;
|
|
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
int fpMaxVal = 0x4F000000; // 2.14748365E9f (2147483648)
|
|
|
|
Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
|
|
|
|
Operand nIntOrLong = context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes);
|
|
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nIntOrLong2 = context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
Operand nInt = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, nRes);
|
|
|
|
Operand dRes;
|
|
if (signed)
|
|
{
|
|
dRes = context.BitwiseExclusiveOr(nIntOrLong, nInt);
|
|
}
|
|
else
|
|
{
|
|
dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
|
|
dRes = context.Add(dRes, nIntOrLong);
|
|
}
|
|
|
|
InsertScalar(context, op.Vd, dRes);
|
|
}
|
|
else
|
|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
if (roundMode != FPRoundingMode.ToNearestAway)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundsd, nRes, Const(X86GetRoundControl(roundMode)));
|
|
}
|
|
else
|
|
{
|
|
nRes = EmitSse41RoundToNearestWithTiesToAwayOpF(context, nRes, scalar: true);
|
|
}
|
|
|
|
Operand zero = context.VectorZero();
|
|
|
|
Operand nCmp;
|
|
Operand nIntOrLong2 = default;
|
|
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
long fpMaxVal = 0x41E0000000000000L; // 2147483648.0000000d (2147483648)
|
|
|
|
Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
|
|
|
|
Operand nIntOrLong = context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes);
|
|
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nIntOrLong2 = context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
Operand nLong = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, nRes);
|
|
nLong = context.ConvertI64ToI32(nLong);
|
|
|
|
Operand dRes;
|
|
if (signed)
|
|
{
|
|
dRes = context.BitwiseExclusiveOr(nIntOrLong, nLong);
|
|
}
|
|
else
|
|
{
|
|
dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
|
|
dRes = context.Add(dRes, nIntOrLong);
|
|
}
|
|
|
|
InsertScalar(context, op.Vd, dRes);
|
|
}
|
|
}
|
|
|
|
private static void EmitSse41ConvertVector32(ArmEmitterContext context, FPRoundingMode roundMode, bool signed)
|
|
{
|
|
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
|
|
|
EmitVectorUnaryOpSimd32(context, (n) =>
|
|
{
|
|
int sizeF = op.Size & 1;
|
|
|
|
if (sizeF == 0)
|
|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundps, nRes, Const(X86GetRoundControl(roundMode)));
|
|
|
|
Operand zero = context.VectorZero();
|
|
Operand nCmp;
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
Operand fpMaxValMask = X86GetAllElements(context, 0x4F000000); // 2.14748365E9f (2147483648)
|
|
|
|
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
|
|
Operand nInt2 = default;
|
|
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
if (signed)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Pxor, nInt, nRes);
|
|
}
|
|
else
|
|
{
|
|
Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
|
|
return context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
|
|
}
|
|
}
|
|
else /* if (sizeF == 1) */
|
|
{
|
|
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Roundpd, nRes, Const(X86GetRoundControl(roundMode)));
|
|
|
|
Operand zero = context.VectorZero();
|
|
Operand nCmp;
|
|
if (!signed)
|
|
{
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
}
|
|
|
|
Operand fpMaxValMask = X86GetAllElements(context, 0x43E0000000000000L); // 9.2233720368547760E18d (9223372036854775808)
|
|
|
|
Operand nLong = InstEmit.EmitSse2CvtDoubleToInt64OpF(context, nRes, false);
|
|
Operand nLong2 = default;
|
|
|
|
if (!signed)
|
|
{
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
|
|
|
|
nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
|
|
|
|
nLong2 = InstEmit.EmitSse2CvtDoubleToInt64OpF(context, nRes, false);
|
|
}
|
|
|
|
nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
|
|
|
|
if (signed)
|
|
{
|
|
return context.AddIntrinsic(Intrinsic.X86Pxor, nLong, nRes);
|
|
}
|
|
else
|
|
{
|
|
Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
|
|
return context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
|
|
}
|
|
}
|
|
});
|
|
}
|
|
}
|
|
}
|