Ryujinx/ChocolArm64/Instruction
LDj3SNuD 42e4e02a64 Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs

* Update AInstEmitSimdCvt.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Add QCFlagBit.

* Add QCFlagBit.
2018-09-01 11:52:51 -03:00
..
ACryptoHelper.cs
AInst.cs
AInstEmitAlu.cs
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs
AInstEmitFlow.cs
AInstEmitHash.cs
AInstEmitMemory.cs
AInstEmitMemoryEx.cs
AInstEmitMemoryHelper.cs
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) 2018-09-01 11:52:51 -03:00
AInstEmitSimdCmp.cs
AInstEmitSimdCrypto.cs
AInstEmitSimdCvt.cs Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) 2018-09-01 11:52:51 -03:00
AInstEmitSimdHash.cs
AInstEmitSimdHelper.cs
AInstEmitSimdLogical.cs
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs
AInstEmitSimdShift.cs
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs
ASoftFallback.cs
ASoftFloat.cs
AVectorHelper.cs