mirror of
https://github.com/Ryujinx/Ryujinx.git
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a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
246 lines
8.5 KiB
C#
246 lines
8.5 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using System;
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using System.Collections.Generic;
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namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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class CopyResolver
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{
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private class ParallelCopy
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{
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private struct Copy
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{
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public Register Dest { get; }
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public Register Source { get; }
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public OperandType Type { get; }
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public Copy(Register dest, Register source, OperandType type)
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{
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Dest = dest;
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Source = source;
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Type = type;
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}
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}
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private List<Copy> _copies;
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public int Count => _copies.Count;
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public ParallelCopy()
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{
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_copies = new List<Copy>();
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}
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public void AddCopy(Register dest, Register source, OperandType type)
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{
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_copies.Add(new Copy(dest, source, type));
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}
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public void Sequence(List<Operation> sequence)
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{
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Dictionary<Register, Register> locations = new Dictionary<Register, Register>();
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Dictionary<Register, Register> sources = new Dictionary<Register, Register>();
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Dictionary<Register, OperandType> types = new Dictionary<Register, OperandType>();
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Queue<Register> pendingQueue = new Queue<Register>();
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Queue<Register> readyQueue = new Queue<Register>();
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foreach (Copy copy in _copies)
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{
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locations[copy.Source] = copy.Source;
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sources[copy.Dest] = copy.Source;
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types[copy.Dest] = copy.Type;
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pendingQueue.Enqueue(copy.Dest);
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}
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foreach (Copy copy in _copies)
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{
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// If the destination is not used anywhere, we can assign it immediately.
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if (!locations.ContainsKey(copy.Dest))
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{
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readyQueue.Enqueue(copy.Dest);
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}
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}
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while (pendingQueue.TryDequeue(out Register current))
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{
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Register copyDest;
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Register origSource;
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Register copySource;
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while (readyQueue.TryDequeue(out copyDest))
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{
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origSource = sources[copyDest];
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copySource = locations[origSource];
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OperandType type = types[copyDest];
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EmitCopy(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
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locations[origSource] = copyDest;
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if (origSource == copySource && sources.ContainsKey(origSource))
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{
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readyQueue.Enqueue(origSource);
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}
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}
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copyDest = current;
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origSource = sources[copyDest];
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copySource = locations[origSource];
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if (copyDest != copySource)
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{
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OperandType type = types[copyDest];
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type = type.IsInteger() ? OperandType.I64 : OperandType.V128;
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EmitXorSwap(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
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locations[origSource] = copyDest;
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Register swapOther = copySource;
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if (copyDest != locations[sources[copySource]])
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{
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// Find the other swap destination register.
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// To do that, we search all the pending registers, and pick
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// the one where the copy source register is equal to the
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// current destination register being processed (copyDest).
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foreach (Register pending in pendingQueue)
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{
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// Is this a copy of pending <- copyDest?
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if (copyDest == locations[sources[pending]])
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{
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swapOther = pending;
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break;
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}
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}
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}
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// The value that was previously at "copyDest" now lives on
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// "copySource" thanks to the swap, now we need to update the
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// location for the next copy that is supposed to copy the value
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// that used to live on "copyDest".
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locations[sources[swapOther]] = copySource;
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}
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}
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}
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private static void EmitCopy(List<Operation> sequence, Operand x, Operand y)
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{
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sequence.Add(new Operation(Instruction.Copy, x, y));
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}
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private static void EmitXorSwap(List<Operation> sequence, Operand x, Operand y)
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{
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sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, x, x, y));
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sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, y, y, x));
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sequence.Add(new Operation(Instruction.BitwiseExclusiveOr, x, x, y));
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}
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}
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private Queue<Operation> _fillQueue = new Queue<Operation>();
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private Queue<Operation> _spillQueue = new Queue<Operation>();
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private ParallelCopy _parallelCopy;
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public bool HasCopy { get; private set; }
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public CopyResolver()
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{
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_fillQueue = new Queue<Operation>();
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_spillQueue = new Queue<Operation>();
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_parallelCopy = new ParallelCopy();
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}
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public void AddSplit(LiveInterval left, LiveInterval right)
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{
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if (left.Local != right.Local)
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{
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throw new ArgumentException("Intervals of different variables are not allowed.");
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}
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OperandType type = left.Local.Type;
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if (left.IsSpilled && !right.IsSpilled)
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{
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// Move from the stack to a register.
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AddSplitFill(left, right, type);
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}
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else if (!left.IsSpilled && right.IsSpilled)
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{
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// Move from a register to the stack.
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AddSplitSpill(left, right, type);
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}
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else if (!left.IsSpilled && !right.IsSpilled && left.Register != right.Register)
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{
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// Move from one register to another.
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AddSplitCopy(left, right, type);
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}
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else if (left.SpillOffset != right.SpillOffset)
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{
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// This would be the stack-to-stack move case, but this is not supported.
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throw new ArgumentException("Both intervals were spilled.");
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}
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}
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private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type)
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{
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Operand register = GetRegister(right.Register, type);
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Operand offset = new Operand(left.SpillOffset);
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_fillQueue.Enqueue(new Operation(Instruction.Fill, register, offset));
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HasCopy = true;
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}
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private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type)
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{
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Operand offset = new Operand(right.SpillOffset);
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Operand register = GetRegister(left.Register, type);
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_spillQueue.Enqueue(new Operation(Instruction.Spill, null, offset, register));
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HasCopy = true;
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}
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private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type)
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{
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_parallelCopy.AddCopy(right.Register, left.Register, type);
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HasCopy = true;
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}
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public Operation[] Sequence()
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{
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List<Operation> sequence = new List<Operation>();
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while (_spillQueue.TryDequeue(out Operation spillOp))
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{
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sequence.Add(spillOp);
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}
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_parallelCopy.Sequence(sequence);
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while (_fillQueue.TryDequeue(out Operation fillOp))
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{
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sequence.Add(fillOp);
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}
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return sequence.ToArray();
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}
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private static Operand GetRegister(Register reg, OperandType type)
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{
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return new Operand(reg.Index, reg.Type, type);
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}
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}
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} |