LDj3SNuD fa5545aab8 Implement Ssubw_V and Usubw_V instructions. (#287) ... * Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdCmp.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs		2018-07-18 21:06:28 -03:00
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AInst.cs
AInstEmitAlu.cs
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs
AInstEmitFlow.cs
AInstEmitHash.cs
AInstEmitMemory.cs
AInstEmitMemoryEx.cs	Fix LDXP/LDAXP when Rt == Rn (#274)	2018-07-16 15:57:15 -03:00
AInstEmitMemoryHelper.cs
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs	Implement Ssubw_V and Usubw_V instructions. (#287)	2018-07-18 21:06:28 -03:00
AInstEmitSimdCmp.cs	Implement Ssubw_V and Usubw_V instructions. (#287)	2018-07-18 21:06:28 -03:00
AInstEmitSimdCvt.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdHelper.cs	Implement Ssubw_V and Usubw_V instructions. (#287)	2018-07-18 21:06:28 -03:00
AInstEmitSimdLogical.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdMemory.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdMove.cs	Implement Ssubw_V and Usubw_V instructions. (#287)	2018-07-18 21:06:28 -03:00
AInstEmitSimdShift.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs
ASoftFallback.cs	Improve CountLeadingZeros() algorithm, nits. (#219)	2018-07-14 15:07:44 -03:00
ASoftFloat.cs
AVectorHelper.cs