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Ryujinx/ChocolArm64/Instruction
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LDj3SNuD 873a7cd112 Add Cls Instruction. (#67) 
* Update AInstEmitAlu.cs

* Update ASoftFallback.cs

* Update AOpCodeTable.cs
2018-03-23 22:06:05 -03:00
..
AInst.cs
AInstEmitAlu.cs Add Cls Instruction. (#67) 2018-03-23 22:06:05 -03:00
AInstEmitAluHelper.cs Fix corner cases of ADCS and SBFM 2018-02-26 15:56:34 -03:00
AInstEmitBfm.cs Fix corner cases of ADCS and SBFM 2018-02-26 15:56:34 -03:00
AInstEmitCcmp.cs
AInstEmitCsel.cs Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store 2018-02-25 22:14:58 -03:00
AInstEmitException.cs Allow more than one process, free resources on process dispose, implement SvcExitThread 2018-03-12 01:14:12 -03:00
AInstEmitFlow.cs Improve CPU initial translation speeds (#50) 2018-03-04 14:09:59 -03:00
AInstEmitHash.cs Remove unused function from CPU 2018-03-14 00:57:07 -03:00
AInstEmitMemory.cs
AInstEmitMemoryEx.cs
AInstEmitMemoryHelper.cs Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks 2018-03-10 20:39:16 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add Frint Instructions and Tests (#62) 2018-03-23 07:40:23 -03:00
AInstEmitSimdCmp.cs Add EXT, CMTST (vector) and UMULL (vector) instructions 2018-03-02 19:23:38 -03:00
AInstEmitSimdCvt.cs Add MUL (vector by element), fix FCVTN, make svcs use MakeError too 2018-03-05 16:18:37 -03:00
AInstEmitSimdHelper.cs Add MLA (vector by element), fixes some cases of MUL (vector by element)? 2018-03-15 22:36:47 -03:00
AInstEmitSimdLogical.cs Add BFI instruction, even more audout fixes 2018-03-16 00:42:44 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs Add SMLAL (vector), fix EXT instruction 2018-03-06 21:36:49 -03:00
AInstEmitSimdShift.cs CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
AInstEmitSystem.cs Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count 2018-03-13 21:24:32 -03:00
AInstEmitter.cs
ASoftFallback.cs Add Cls Instruction. (#67) 2018-03-23 22:06:05 -03:00