mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-19 21:52:22 +00:00
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
399 lines
12 KiB
C#
399 lines
12 KiB
C#
#define SimdImm
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdImm")]
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public sealed class CpuTestSimdImm : CpuTest
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{
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#if SimdImm
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#region "Helper methods"
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// abcdefgh -> aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
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private static ulong ExpandImm8(byte imm8)
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{
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ulong imm64 = 0ul;
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for (int i = 0, j = 0; i < 8; i++, j += 8)
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{
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if (((imm8 >> i) & 0b1) != 0)
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{
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imm64 |= 0b11111111ul << j;
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}
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}
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return imm64;
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}
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// aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh -> abcdefgh
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private static byte ShrinkImm64(ulong imm64)
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{
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byte imm8 = 0;
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for (int i = 0, j = 0; i < 8; i++, j += 8)
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{
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if (((imm64 >> j) & 0b11111111ul) != 0ul) // Note: no format check.
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{
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imm8 |= (byte)(0b1 << i);
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}
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}
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return imm8;
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}
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<byte> _8BIT_IMM_()
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{
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yield return 0x00;
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yield return 0x7F;
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yield return 0x80;
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yield return 0xFF;
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for (int cnt = 1; cnt <= RndCntImm8; cnt++)
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{
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byte imm8 = TestContext.CurrentContext.Random.NextByte();
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yield return imm8;
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}
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}
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private static IEnumerable<ulong> _64BIT_IMM_()
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{
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yield return ExpandImm8(0x00);
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yield return ExpandImm8(0x7F);
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yield return ExpandImm8(0x80);
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yield return ExpandImm8(0xFF);
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for (int cnt = 1; cnt <= RndCntImm64; cnt++)
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{
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byte imm8 = TestContext.CurrentContext.Random.NextByte();
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yield return ExpandImm8(imm8);
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Bic_Orr_Vi_16bit_()
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{
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return new uint[]
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{
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0x2F009400u, // BIC V0.4H, #0
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0x0F009400u // ORR V0.4H, #0
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};
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}
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private static uint[] _Bic_Orr_Vi_32bit_()
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{
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return new uint[]
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{
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0x2F001400u, // BIC V0.2S, #0
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0x0F001400u // ORR V0.2S, #0
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};
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}
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private static uint[] _F_Mov_Vi_2S_()
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{
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return new uint[]
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{
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0x0F00F400u // FMOV V0.2S, #2.0
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};
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}
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private static uint[] _F_Mov_Vi_4S_()
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{
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return new uint[]
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{
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0x4F00F400u // FMOV V0.4S, #2.0
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};
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}
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private static uint[] _F_Mov_Vi_2D_()
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{
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return new uint[]
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{
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0x6F00F400u // FMOV V0.2D, #2.0
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};
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}
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private static uint[] _Movi_V_8bit_()
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{
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return new uint[]
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{
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0x0F00E400u // MOVI V0.8B, #0
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};
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}
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private static uint[] _Movi_Mvni_V_16bit_shifted_imm_()
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{
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return new uint[]
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{
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0x0F008400u, // MOVI V0.4H, #0
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0x2F008400u // MVNI V0.4H, #0
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};
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}
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private static uint[] _Movi_Mvni_V_32bit_shifted_imm_()
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{
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return new uint[]
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{
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0x0F000400u, // MOVI V0.2S, #0
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0x2F000400u // MVNI V0.2S, #0
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};
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}
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private static uint[] _Movi_Mvni_V_32bit_shifting_ones_()
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{
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return new uint[]
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{
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0x0F00C400u, // MOVI V0.2S, #0, MSL #8
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0x2F00C400u // MVNI V0.2S, #0, MSL #8
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};
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}
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private static uint[] _Movi_V_64bit_scalar_()
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{
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return new uint[]
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{
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0x2F00E400u // MOVI D0, #0
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};
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}
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private static uint[] _Movi_V_64bit_vector_()
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{
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return new uint[]
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{
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0x6F00E400u // MOVI V0.2D, #0
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};
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntImm8 = 2;
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private const int RndCntImm64 = 2;
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[Test, Pairwise]
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public void Bic_Orr_Vi_16bit([ValueSource("_Bic_Orr_Vi_16bit_")] uint opcodes,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 13);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Bic_Orr_Vi_32bit([ValueSource("_Bic_Orr_Vi_32bit_")] uint opcodes,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 3) << 13);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2S([ValueSource("_F_Mov_Vi_2S_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_4S([ValueSource("_F_Mov_Vi_4S_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Mov_Vi_2D([ValueSource("_F_Mov_Vi_2D_")] uint opcodes,
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[Range(0u, 255u, 1u)] uint abcdefgh)
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{
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uint abc = (abcdefgh & 0xE0u) >> 5;
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uint defgh = (abcdefgh & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_V_8bit([ValueSource("_Movi_V_8bit_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_16bit_shifted_imm([ValueSource("_Movi_Mvni_V_16bit_shifted_imm_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <0, 8>
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 13);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifted_imm([ValueSource("_Movi_Mvni_V_32bit_shifted_imm_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 3) << 13);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_Mvni_V_32bit_shifting_ones([ValueSource("_Movi_Mvni_V_32bit_shifting_ones_")] uint opcodes,
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[ValueSource("_8BIT_IMM_")] byte imm8,
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[Values(0b0u, 0b1u)] uint amount, // <8, 16>
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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opcodes |= ((amount & 1) << 12);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(q == 0u ? z : 0ul);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_V_64bit_scalar([ValueSource("_Movi_V_64bit_scalar_")] uint opcodes,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE1(z);
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SingleOpcode(opcodes, v0: v0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Movi_V_64bit_vector([ValueSource("_Movi_V_64bit_vector_")] uint opcodes,
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[ValueSource("_64BIT_IMM_")] ulong imm)
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{
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byte imm8 = ShrinkImm64(imm);
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uint abc = (imm8 & 0xE0u) >> 5;
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uint defgh = (imm8 & 0x1Fu);
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opcodes |= (abc << 16) | (defgh << 5);
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SingleOpcode(opcodes);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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